RF switching circuitry includes one or more RF switching elements, a control signal input node, a common resistor, and common resistor bypass circuitry. The one or more RF switching elements are coupled in series between a switch input node and a switch output node. A state of each one of the one or more switching elements is determined based on a control signal. The control signal input node is configured to receive the control signal. The common resistor is coupled between the control signal input node and the one or more RF switching elements. The common resistor bypass circuitry is configured to receive the switching control signal and bypass the common resistor for a predetermined time period following one or more of a leading edge of the switching control signal and a falling edge of the switching control signal.

An integrated circuit (IC) includes a level shifter coupled to receive a first supply voltage and a second supply voltage and configured to generate a first output signal and a second output signal in response to an input command signal and an edge detector configured to detect an edge on the second supply voltage and to sink a current from the level shifter in response to detection of the edge in order to prevent a change in logic state of the first output signal or the second output signal. The edge detector can include a positive edge detector configured to generate a positive edge signal in response to detection of a positive going edge of greater than a first predetermined slew rate and a negative edge detector configured to generate a negative edge signal in response to detection of a negative going edge of greater than a second predetermined slew rate.

An integrated circuit (IC) includes a level shifter coupled to receive a first supply voltage and a second supply voltage and configured to generate a first output signal and a second output signal in response to an input command signal and an edge detector configured to detect an edge on the second supply voltage and to sink a current from the level shifter in response to detection of the edge in order to prevent a change in logic state of the first output signal or the second output signal. The edge detector can include a positive edge detector configured to generate a positive edge signal in response to detection of a positive going edge of greater than a first predetermined slew rate and a negative edge detector configured to generate a negative edge signal in response to detection of a negative going edge of greater than a second predetermined slew rate.

A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

Disclosed is a dual clock signal to pulse-width modulated signal conversion circuit, comprising: a first counter, an input end of which inputs a first clock signal, and an output end of which outputs a divided signal; an edge reset circuit, an input end of which inputs the divided signal, the output end of which outputs a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; a second counter, an input end of which inputs the second clock signal and the first reset pulse signal, and an output end of which outputs the first pulse-width modulated signal; a third counter, an input end of which inputs the second clock signal and the second reset pulse signal, and an output end of which outputs the second pulse-width modulated signal; a logic processing circuit, an input end of which inputs the first pulse-width modulated signal and the second pulse-width modulated signal, and an output end of which outputs a pulse-width modulated signal PWM_OUT. The disclosure offers high precision, system stability, and good anti-interference.

Disclosed is a dual clock signal to pulse-width modulated signal conversion circuit, comprising: a first counter, an input end of which inputs a first clock signal, and an output end of which outputs a divided signal; an edge reset circuit, an input end of which inputs the divided signal, the output end of which outputs a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; a second counter, an input end of which inputs the second clock signal and the first reset pulse signal, and an output end of which outputs the first pulse-width modulated signal; a third counter, an input end of which inputs the second clock signal and the second reset pulse signal, and an output end of which outputs the second pulse-width modulated signal; a logic processing circuit, an input end of which inputs the first pulse-width modulated signal and the second pulse-width modulated signal, and an output end of which outputs a pulse-width modulated signal PWM_OUT. The disclosure offers high precision, system stability, and good anti-interference.

A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.