Circuits and methods to mitigate or eliminate potentially damaging events (e.g., damaging current spikes from in-rush current, charge transfer current, short circuits, etc.) in DC-DC power converters. Embodiments enable dynamic switching of conversion ratios in reconfigurable power converters while under load without turning off the power converter circuitry or suspending switching of the charge pump power switches. Embodiments selectively increase the ON resistance, R.sub.ON, for at least some power FETs in a power converter by actively controlling the driver voltage to the gates of the power FETs. During normal operation, the power FET driver voltage may be set to overdrive the FET gate to lower R.sub.ON to a desired level that allows high current flow. For other scenarios, the power FET driver voltage may be reduced so as to increase R.sub.ON while ON and thus impede current flow to provide protection against potentially damaging events.

Provided is a driver circuit that controls an output unit that switches whether or not to supply a current to an output line, in accordance with a potential difference between a first control signal to be input and a voltage of the output line. The driver circuit comprises a control line that transmits the first control signal to the output unit; a low potential line to which a predetermined reference potential is applied; a first connection switching unit that switches whether or not to connect the control line and the low potential line, in accordance with a second control signal; and a cutoff unit that is provided in series with the first connection switching unit between the control line and the low potential line and cuts off the control line and the low potential line based on a potential of the low potential line.

An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a highpass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.

A control unit has an input with a positive and negative connectors. The control unit also includes an output and with an electronic switch. The switch has a first connector, a second connector and a control connector, and has an on-state resistance between its first and second connector that depends on a control voltage at the control connector of the switch. The first connector is connected to the connector for the positive potential of the input, the second connector is connected to the connector for the positive potential of the output, and the control connector is connected to a trigger circuit. A second controllable switch is also included with a first connector connected to the second connector of the first switch, a second connector connected to the control connector of the first switch, and a control connector connected to the connector for the negative potential of the input.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During the standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During the standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.

According to one aspect of embodiments, a drive circuit of a normally-ON transistor includes: a normally-OFF transistor that includes a main current path connected in serial to a main current path of the normally-ON transistor; and a buffer circuit that supplies, to a gate of the normally-ON transistor, a control signal for controlling turning ON and OFF of the normally-ON transistor, whose high-voltage side and low-voltage side are biased by a bias voltage supplied from a power source unit.

A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a drift region (11) in the semiconductor body (100); a plurality of transistor cells (10); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells (10) includes: a first trench electrode (21) insulated from the semiconductor body (100) by a first dielectric layer (22); a second trench electrode (23) insulated from the semiconductor body (100) by a second dielectric layer (24); a source region (13) and a body region (14) in a first mesa region (111) between the first trench electrode (21) and the second trench electrode (23); and a compensation region (12), wherein the compensation region (12) adjoins the body region (14), the first dielectric (22), the second dielectric (24), and forms a pn-junction with the drift region (11), and wherein from the first trench electrode (21) and the second trench electrode (23) at least the first trench electrode (21) is connected to the gate node (G).

A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative V.sub.GS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the V.sub.GS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.

According to one embodiment, a semiconductor protection circuit includes a first MOS transistor that has a drain that is connected to an input terminal, a source that is connected to an output terminal, and a gate that is connected to a control terminal, a second MOS transistor that has a drain that is connected to the gate of the first MOS transistor and a source that is connected to the source of the first MOS transistor, a rectifier element that is connected in a forward direction from a gate of the second MOS transistor to the gate of the first MOS transistor, and a low-pass filter that is connected between the gate and the source of the second MOS transistor.