A battery disconnecting device has a first input and a second input to which a battery can be connected, whereby the disconnecting device also has a first output and a second output to which an electric component can be connected, whereby at least one first circuit breaker is arranged between the first input and the first output, and at least one second circuit breaker is arranged between the second input and the second output, whereby the first circuit breaker is at least a transistor and the second circuit breaker is a relay.

Various embodiments include a switching device for disconnecting a current path in a DC supply system, said current path comprising source-end and load-end inductances, comprising: two series-connected switching modules, wherein each of the switching modules comprises a controllable semiconductor switching element connected in parallel to a series circuit with a resistor and a capacitor. Each resistor includes two respective series-connected resistors. A first end of the respective resistor is connected to a first load terminal of the controllable semiconductor switching element and a second end of the respective resistor is connected to the capacitor. Each of the switching modules comprises a further controllable semiconductor switching element connected between a first node of the two resistors in the respective resistor and a second node connects the capacitor to a second load terminal of the controllable semiconductor switching element.

An embodiment of a semiconductor device includes a plurality of transistor sections separated from each other and a plurality of diode sections separated from each other. Each transistor section includes an emitter electrode and a collector electrode. Each diode section includes an anode electrode and a cathode electrode. Each transistor section is electrically coupled to a common gate pad. A ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections.

Current imbalances between parallel switching devices in a power converter half leg are reduced. A gate driver generates a nominal PWM gate drive signal for a respective half leg. A first feedback loop couples the nominal PWM gate drive signal to a gate terminal of a respective first switching device. The first feedback loop has a first mutual inductance with a current path of a first parallel switching device and has a second mutual inductance with a current path of a second parallel switching device. The first and second mutual inductances are arranged to generate opposing voltages in the first feedback loop, so that when all the parallel switching devices carry equal current then the voltages cancel.

A semiconductor module comprises reverse conducting IGBT connected in parallel with a wide bandgap MOSFET, wherein each of the reverse conducting IGBT and the wide bandgap MOSFET comprises an internal anti-parallel diode. A method for operating a semiconductor module with the method including the steps of: determining a reverse conduction start time, in which the semiconductor module starts to conduct a current in a reverse direction, which reverse direction is a conducting direction of the internal anti-parallel diodes; applying a positive gate signal to the wide bandgap MOSFET after the reverse conduction start time; determining a reverse conduction end time based on the reverse conduction start time, in which the semiconductor module ends to conduct a current in the reverse direction; and applying a reduced gate signal to the wide bandgap MOSFET a blanking time interval before the reverse conduction end time, the reduced gate signal being adapted for switching the wide bandgap MOSFET into a blocking state.

A method comprises configuring a power converter to operate as a boost converter, the power converter comprising a low side switch and a high side switch, during a first dead time after turning off the low side switch and before turning on the high side switch, configuring the power converter such that a current of the power converter flows through a high speed diode, and after turning on the high side switch, configuring the power converter such that the current of the power converter flows through a low forward voltage drop diode.

A gate driver system includes a gate driver having a first input for receiving a digital input signal, a second input for receiving a short circuit protection signal, and output for driving a power device; a current reconstruction circuit having a first input for receiving a voltage across an inductance associated with the power device, a second input for receiving a current associated with the power device, a third input for receiving the digital input signal, and an output for providing a sensed power device current; and a comparator having a first input coupled to the output of the current reconstruction circuit, a second input coupled to a reference, and an output coupled to the second input of the gate driver.

A power device driving apparatus drives a plurality of power devices including first and second power devices. In the apparatus, a plurality of drive circuits are separately provided for at least the first power device and the second power device and output drive signals to the respective power devices. The isolated power supply includes a first isolated power supply unit that supplies a first supply voltage, and a second isolated power supply unit that supplies a second supply voltage that is different from the first supply voltage. The plurality of drive circuits includes a first drive circuit that uses the first supply voltage supplied from the first isolated power supply unit to output the drive signal to the first power device, and a second drive circuit that uses the second supply voltage supplied from the second isolated power supply unit to output the drive signal to the second power device.

A hybrid drive circuit (100, 100′) drives a first characteristic transistor and a second characteristic transistor coupled in parallel to the first characteristic transistor according to an input signal (Sin). The hybrid drive circuit (100, 100′) includes a first turn-on path (Pc1), a first turn-off path (Ps1), a second turn-on path (Pc2), and a second turn-off path (Ps2). The first turn-on path (Pc1) and the second turn-on path (Pc2) produce a first delay time to delay turning on the first characteristic transistor. The first turn-off path (Ps1) and the second turn-off path (Ps2) produce a second delay time to delay turning off the second characteristic transistor.

A plurality of drive circuits each drive a corresponding one of a plurality of power semiconductor elements connected in parallel. Each of the drive circuits includes a control command unit, a current detector, a differentiator, and an integrator. The current detector detects a gate current that flows into a gate terminal of a corresponding one of the power semiconductor elements after the control command unit outputs a turn-on command. The differentiator performs time differentiation of the gate current detected by the current detector. The integrator performs time integration of the gate current detected by the current detector. Based on a differential value and an integral value in each of the drive circuits, the determination unit determines whether an overcurrent state occurs or not in any of the plurality of power semiconductor elements.