Systems, circuits, and methods for operating an Insulated-Gate Bipolar Transistor (IGBT) are provided. A circuit is to include a first driver for the IGBT, the first driver having a first resistance and being connectable to the gate of the IGBT. The circuit is further described to include a second driver for the IGBT, the second driver having a second resistance different from the first resistance and also being connectable to the gate of the IGBT. The circuit is also described to include a controller that receives at least two inputs regarding operating characteristics of the IGBT and based on the at least two inputs decides whether to connect the first or second driver to the gate of the IGBT during power-down of the IGBT.

The present disclosure relates to a compensation circuit for independently controlling turn-on and turn-off of a power electronic switch through a gate driver. The compensation circuit includes a circuit path sampling a first portion of a voltage induced across an inductance of the power electronic switch at turn-on. Another circuit path samples a second portion of the voltage induced across the inductance of the power electronic switch at turn-off. The compensation circuit further includes a gate driver reference connection configured to respectively supply the sampled portions of the voltage during turn-on and turn-off of the power electronic switch. A compensation circuit controlling a first power electronic switch in parallel with a second power electronic switch, a commutation cell and a power converter having a pair of parallel legs, in which each power electronic switch is provided with the compensation circuit, are also disclosed.

Disclosed herein is a power electronic device assembly for preventing parasitic switching-on of a feeder circuit breaker. The assembly includes a logic circuit, a power switch with an input and a reference leg, and a driver circuit which drives the power switch. The driver circuit includes a drive unit and a short circuit having a safety function. When the input of the power switch is not operated, the power switch is short-circuited by the reference leg so that the potential of the input decreases below a switching-on threshold. An additional wire connection device is disposed between the driver circuit and the power switch and configured such that when no or excessively small amount of supply voltage is applied, the input of the power switch is short-circuited or is coupled to a safety potential at which discharge is secured, whereby discharge of parasitic charge current is secured.

A vehicle includes an electric machine, an IGBT, and a gate driver. The IGBT has a gate, an emitter, and a collector and is configured to flow an electric charge through a phase of the electric machine. The gate driver is configured to flow current onto the gate at a first level, and in response to a time integral of a voltage across the phase exceeding a predetermined level, transition from the first level to a second level less than the first level.

A power drive circuit includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weighting unit, and a comparator. Each gate driver includes a drive resistance setting value. The waveform processing unit outputs a current absolute value waveform of an AC power. The weighting unit generates a trigger voltage. When the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each of the gate drivers. When the gate driver receives the slew rate control signal, each of the gate drivers decreases the drive resistance setting value of the gate driver.

A method for avoiding parasitic oscillation in a parallel semiconductor switch includes allowing only one of the plurality of power components to control a turn-on transition of the semiconductor switch and allowing only one of the plurality of power components to control a turn-off transition of the semiconductor switch, by setting unbalanced driving impedances for the plurality of power components coupled in parallel. Parasitic oscillation in a switch transition may be avoided without impedance matching, and the switch transition may provide a relatively small impact on switch characteristics.

Provided is a gate driving apparatus, including: a gate driving unit for driving a gate of a switching device; a switching unit for switching a gate current of the switching device during, within a turn-on period of the switching device, at least a part of the period, which is after timing when a current starts to flow in the switching device, to a smaller current when compared to the gate current before at least a part of the period.

A semiconductor switch device includes a switchable power semiconductor and a control circuit. The semiconductor switch device has a current sink and a current amplifier designed to amplify during a switching process a partial current of the total current flowing across the control capacitor that is not discharged by the current sink up to an adjustable maximum current and to apply the amplified partial current to the control electrode of the power semiconductor so as to counteract the change in the voltage across the collector-emitter path or the drain-source path of the power semiconductor during the switching process. An additional circuit provides an adapted switch-on transition by smoothing the collector voltage and/or the drain voltage of the switchable power semiconductor when switching over the collector-emitter path or the drain-source path of the power semiconductor from a blocked state into a conductive state.

A semiconductor device includes first and second electrodes, a semiconductor part therebetween and first to third control electrodes between the first electrode and the semiconductor part. The semiconductor part includes first and third layers of a first-conductivity-type and second and fourth layers of a second-conductivity-type. The second, third and fourth layers are provided between the first layer and the first electrode, between the second layer and the first electrode, and between the first layer and the second electrode, respectively. To the first to third control electrodes, first to third voltages greater than the threshold voltage thereof are applied at first to third timings, respectively. The third, second and first voltages are reduced to a lower level than the threshold voltage at a fourth timing after the first to third timings, at a fifth timing after the fourth timing and at a sixth timing after the fifth timing, respectively.

A drive circuit of a power semiconductor element comprises a gate drive voltage generator to generate, based on an ON/OFF drive timing signal input to an input terminal, a gate drive voltage to be applied to a gate electrode of a switching element having the gate electrode for controlling a main current that flows between a first main electrode and a second main electrode, wherein the gate drive voltage generator includes a gate current limiting circuit in which a current limiter to limit a current and a voltage limiter to limit the magnitude of a voltage applied to both ends of the current limiter are connected in parallel.