A potential generating circuit includes a first transistor and a second transistor. Potential at a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the potential generating circuit. Potential at a substrate of the second transistor varies with the first parameter. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as a first output of the potential generating circuit. A gate of the second transistor is connected to a drain of the second transistor. The substrate of the second transistor serves as a second output of the potential generating circuit.

A potential generating circuit includes a first transistor and a second transistor. Potential at a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the potential generating circuit. Potential at a substrate of the second transistor varies with the first parameter. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as a first output of the potential generating circuit. A gate of the second transistor is connected to a drain of the second transistor. The substrate of the second transistor serves as a second output of the potential generating circuit.

Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.

A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD−X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.

A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g.Math.μ.sub.B.Math.B>min(Δ(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that Δ(Vbg)<g.Math.μ.sub.B.Math.B+2|M.sub.SO|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Landé factor, μ.sub.B corresponding to a Bohr magneton, Δ corresponding to an intervalley energy difference in the semiconducting portion, and M.sub.SO corresponding to the intervalley spin-orbit coupling.

Disclosed are a memory interface circuit including an output impedance monitor, which is capable of monitoring and calibrating an output impedance of a driving circuit in real time, and a method of calibrating the output impedance. The memory interface circuit includes a control circuit that outputs a digital transmission signal, a driving circuit that outputs an output signal, based on the digital transmission signal, an output impedance monitor that outputs a pull-up monitoring signal or a pull-down monitoring signal, based on the digital transmission signal and the output signal, and an output impedance calibrator that outputs an impedance monitoring signal, based on the pull-up monitoring signal or the pull-down monitoring signal, and wherein the driving circuit calibrates output impedance based on the impedance monitoring signal.

A subsystem interface, a semiconductor device including the subsystem interface, and a communications method of the semiconductor device are provided, the subsystem interface comprising a transmitter including a first transmission port configured to transmit a first clock signal, a second transmission port configured to transmit a first data signal, a first reception port configured to receive a first flow control signal, and a third transmission port configured to transmit a first synchronization signal, a receiver including a second reception port configured to receive a second clock signal, a third reception port configured to receive a second data signal, a fourth transmission port configured to transmit a second flow control signal, a fourth reception port configured to receive a second synchronization signal, and a control module configured to control operations of the transmitter and the receiver, including performing a transmitter hand-shake by sending a request signal from the second transmission port and receiving an acknowledgement signal to the first reception port, or performing a receiver hand-shake by receiving the request signal to the third reception port and sending the acknowledgement signal from the fourth transmission port.

A subsystem interface, a semiconductor device including the subsystem interface, and a communications method of the semiconductor device are provided, the subsystem interface comprising a transmitter including a first transmission port configured to transmit a first clock signal, a second transmission port configured to transmit a first data signal, a first reception port configured to receive a first flow control signal, and a third transmission port configured to transmit a first synchronization signal, a receiver including a second reception port configured to receive a second clock signal, a third reception port configured to receive a second data signal, a fourth transmission port configured to transmit a second flow control signal, a fourth reception port configured to receive a second synchronization signal, and a control module configured to control operations of the transmitter and the receiver, including performing a transmitter hand-shake by sending a request signal from the second transmission port and receiving an acknowledgement signal to the first reception port, or performing a receiver hand-shake by receiving the request signal to the third reception port and sending the acknowledgement signal from the fourth transmission port.

The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.