A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Implementations generally increase the virtual resolution of a camera sensor. In some implementations, a method includes moving an image sensor in a predetermined pattern, wherein the image sensor includes an array of light collecting elements, and wherein each light collecting element of the sensor array cycles through a plurality of positions in the predetermined pattern. The method further includes capturing a plurality of samples of light at each light collecting element, wherein each light collecting element captures a plurality of the samples in a cycle of movement in the predetermined pattern. The method further includes converting each sample captured at each position into a value. The method further includes generating at least one image from an aggregate of values converted from the samples of light.

Implementations generally increase the virtual resolution of a camera sensor. In some implementations, a method includes moving an image sensor in a predetermined pattern, wherein the image sensor includes an array of light collecting elements, and wherein each light collecting element of the sensor array cycles through a plurality of positions in the predetermined pattern. The method further includes capturing a plurality of samples of light at each light collecting element, wherein each light collecting element captures a plurality of the samples in a cycle of movement in the predetermined pattern. The method further includes converting each sample captured at each position into a value. The method further includes generating at least one image from an aggregate of values converted from the samples of light.

A new computational machine is invented, called a clock machine, that is a novel alternative to computing machines (digital computers) based on logic gates. In an embodiment, computation is performed with one or more clock machines that use time, and can perform any Boolean function. In an embodiment, a cryptographic cipher is implemented with random clock machines, constructed from a non-deterministic process, wherein the compiled set of instructions (i.e., the implementation of the cryptographic procedure) is distinct on each device or chip that executes the cryptographic cipher. In an embodiment, by using a different set of clock machines to execute two different instances of the same cryptographic procedure, each execution of a procedure looks different to malware that may try to infect and subvert the cryptographic procedure. This cryptographic process helps hinder timing attacks. In an embodiment, a detailed implementation of the Midori cipher with random clock machines is described.

A new computational machine is invented, called a clock machine, that is a novel alternative to computing machines (digital computers) based on logic gates. In an embodiment, computation is performed with one or more clock machines that use time, and can perform any Boolean function. In an embodiment, a cryptographic cipher is implemented with random clock machines, constructed from a non-deterministic process, wherein the compiled set of instructions (i.e., the implementation of the cryptographic procedure) is distinct on each device or chip that executes the cryptographic cipher. In an embodiment, by using a different set of clock machines to execute two different instances of the same cryptographic procedure, each execution of a procedure looks different to malware that may try to infect and subvert the cryptographic procedure. This cryptographic process helps hinder timing attacks. In an embodiment, a detailed implementation of the Midori cipher with random clock machines is described.

A device including an optoelectric circuit that is configured to provide galvanic isolation between a first circuit and a second circuit is disclosed. The optoelectric circuit includes at least one non-inverting buffer and a metal semiconductor diode. The at least one non-inverting buffer is positioned between a collector of a phototransistor and an anode of a light emitting diode. The metal semiconductor diode is positioned between the collector of the phototransistor and the at least one non-inverting buffer.

A device including an optoelectric circuit that is configured to provide galvanic isolation between a first circuit and a second circuit is disclosed. The optoelectric circuit includes at least one non-inverting buffer and a metal semiconductor diode. The at least one non-inverting buffer is positioned between a collector of a phototransistor and an anode of a light emitting diode. The metal semiconductor diode is positioned between the collector of the phototransistor and the at least one non-inverting buffer.

The present invention relates to a photonic chip realized by combining at least one Programmable Photonics Analog Block (PPAB) and at least one Reconfigurable Photonic Interconnection (RPI) implemented over a photonic chip that is capable of implementing one or various simultaneous photonics circuits and/or linear multipart transformations by the appropriate programming of its resources (i.e. PPABs and RPIs) and the selection of its input and output ports. The invention also relates to a field-programmable photonic array (FPPA) comprising at least a programmable circuit based on tunable beamsplitters with independent coupling and phase-sifting configuration and peripheral high-performance building blocks.

A light receiving unit having a first energy source made up of two sub sources. A first terminal contact is formed at the upper face of the first sub source and a second terminal contact is formed at the lower face of the second sub source. The sub source has at least one semiconductor diode that has an absorption edge adapted to a first wavelength of light and the second semiconductor diode has an absorption edge adapted to a second wavelength of light which is different from the first wavelength of light, such that the first sub source generates electric voltage upon being irradiated with the first wavelength of light and the second sub source generates electric voltage upon being irradiated with the second wavelength of light.

A light receiving unit having a first energy source made up of two sub sources. A first terminal contact is formed at the upper face of the first sub source and a second terminal contact is formed at the lower face of the second sub source. The sub source has at least one semiconductor diode that has an absorption edge adapted to a first wavelength of light and the second semiconductor diode has an absorption edge adapted to a second wavelength of light which is different from the first wavelength of light, such that the first sub source generates electric voltage upon being irradiated with the first wavelength of light and the second sub source generates electric voltage upon being irradiated with the second wavelength of light.