A phase coherent synthesizer with good phase noise and spurious performance is described. The phase coherent synthesizer includes digital direct synthesizer (DDS) circuitry, frequency multiplier circuitry, an oscillator, and a mixing stage. The digital direct synthesizer (DDS) circuitry has a first output and a second output. The first output is associated with a fine resolution synthesis. The second output is associated with a step synthesis. A second output signal provided via the second output has a higher frequency compared with a first output signal provided via the first output. The frequency multiplier circuitry is connected with the second output. The frequency multiplier circuitry is configured to multiply the second output signal received via the second output, thereby generating a multiplied output signal. The mixing stage has two input ports connected with the frequency multiplier circuitry and the oscillator respectively. The mixing stage includes, for example, circuitry configured to mix the multiplied output signal and an oscillator output signal of the oscillator, thereby generating an intermediate frequency signal. The first output signal and the intermediate frequency signal are synchronized with each other.

A frequency synthesis device, including: a first generator configured to generate a periodical signal with a frequency f.sub.1; a second generator, coupled to the first generator and generating from the signal with a frequency f.sub.1 a signal S.sub.G corresponding to a train of oscillations with a frequency substantially equal to N.Math.f.sub.1, with a duration lower than T.sub.1=1/f.sub.1 and periodically repeated at the frequency f.sub.1; a third generator generating, from the signal S.sub.G, m periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm with frequency spectra each include a main line with a frequency f.sub.LO.sub._.sub.CHi corresponding to an integer multiple of f.sub.1, with 1≦i≦m, the third generator operating as a band-pass filter applied to the signal S.sub.G and discarding from the frequency spectra of each of the periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm lines other than the main line with a frequency f.sub.LO.sub._.sub.CHi.

A frequency synthesis device, including: a first generator configured to generate a periodical signal with a frequency f.sub.1; a second generator, coupled to the first generator and generating from the signal with a frequency f.sub.1 a signal S.sub.G corresponding to a train of oscillations with a frequency substantially equal to N.Math.f.sub.1, with a duration lower than T.sub.1=1/f.sub.1 and periodically repeated at the frequency f.sub.1; a third generator generating, from the signal S.sub.G, m periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm with frequency spectra each include a main line with a frequency f.sub.LO.sub._.sub.CHi corresponding to an integer multiple of f.sub.1, with 1≦i≦m, the third generator operating as a band-pass filter applied to the signal S.sub.G and discarding from the frequency spectra of each of the periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm lines other than the main line with a frequency f.sub.LO.sub._.sub.CHi.

A built-in test circuit for testing a system timing margin of a processing device under-test is provided. The processing device includes a controller and first clock circuit, wherein the first clock circuit generates a first clock signal and the first clock signal is a main clock signal provided for operation of the processing device. The built-in test circuit includes a second clock circuit and a logic circuit, both of which are integrated with the processing device. The second clock circuit generates a second clock signal. The logic circuit processes the first and second clock signals and outputs a third clock signal. The third clock signal is used to determine system timing margin of the processing device.

Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.

A circuit for eliminating clock jitter based on reconfigurable multi-phase-locked loops includes multiple phase-locked loops, a data selector and a signal synthesizer. In a case of generating a clock signal with low jitter, output signals of two phase-locked loops are adjusted to be the same in frequency and phase, and output signals of other phase-locked loops are adjusted to be different from each other in frequency. The data selector selects output signals, and the signal synthesizer is enabled to superimpose and then average the first and second selected output signals, so as to obtain a clock signal with jitter eliminated. In a case of generating multiple clock signals with different frequencies, output signals of the multiple phase-locked loops are adjusted to be different from each other in frequency, to obtain multiple clock signals with different frequencies through the data selector without enabling the signal synthesizer.

An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.

A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.