Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

A method and apparatus for decomposition of signals with varying envelope into offset components are disclosed here, that sample the time variant envelope of a single carrier (SC) or a multi-carrier (MC) band limited signal, quantizes the sampled value using N.sub.b quantization bits and decomposes the sample into N.sub.b in-phase and quadrature components that are combined in pairs and modulated to generate a set of N.sub.b offset signals. The pulse shape applied in each offset signal is selected according to the spectral mask needed for the signal and to minimize envelope fluctuations in each offset signal from the set of N.sub.b components.

A DAC current steering circuit includes first and second transistors, respectively coupled to first and second outputs via first and second nodes at their drains, and source coupled to each other and to ground. A gate of the first transistor is coupled to a data input (D), and a gate of the second transistor coupled to a complement of the data input (DB). The circuit further includes first and second bleeder transistors, whose drains are respectively coupled to the first and second nodes, and whose sources are coupled together at a third node, the third node coupled to ground, and first and second bleeder switching transistors, whose drains and sources are each coupled to the third node, a gate of the first bleeder switching transistor coupled to a switching input (S) and a gate of the second bleeder switching transistor coupled to a complement of the switching input (SB).

Some embodiments include a resistor that may be used in audio conversion for an ADC. The resistor may be made up of an n-well as well as a p-well polysilicons. The n-well and p-well polysilicons may include a shallow trench isolator. The n-well and p-well components may be in series with other n-well or p-well components respectively. Similarly, multiple n-well components which are in series, may be in parallel with multiple p-well components.

A device for digitizing an analogue signal, wherein a distortion signal outlet of a distortion signal generator is only coupled to an analogue digital converter by passive components.

A phase-shifted sampling circuit is described. The phase-shifted sampling circuit includes a primary sampler circuit, an ADC circuit, and an equalization circuit. The primary sampler circuit includes an analog signal input, a first signal path, and a second signal path. The equalization circuit includes a primary sampler equalizer sub-circuit. The primary sampler equalizer sub-circuit is configured to compensate a mismatch between a transfer function associated with the first signal path and a transfer function associated with the second signal path. Further, a method of determining filter coefficients of an equalization circuit of a phase-shifted sampling circuit is described.

The present invention provides a device for processing digital signals. The device comprises a digital signal source configured to output codewords, a converter circuit configured to generate an output signal based on a first codeword received from the digital signal source, and a feed forward circuit configured to generate an output current based on a second codeword received from the digital signal source. The output current generated by the feed forward circuit is connected to a current supply of the converter circuit. The digital signal source is configured to generate the second codeword based on the first codeword in order to compensate for variations of a supply current of the converter circuit.

A mechanism is included for jointly determining filter coefficients for Finite Impulse Response (FIR) filters in a Linear, Memory-less Non-linear (LNL), Linear compensator. Calibration signals are applied to a signal converter input in a test and measurement system. Non-linear signal components are determined in signal output from the signal converter. Non-linear filter components are determined at the LNL compensator based on the calibration signals. The non-linear signal components are then compared to the non-linear filter components. The comparison is then resolved to determine filter coefficients for first stage Finite Impulse Response (FIR) filters and second stage FIR filters in the LNL.

Example embodiments relate to systems and methods for analog-to-digital signal conversion. One embodiment includes a system for analog-to-digital signal conversion. The system includes an analog input signal. The system also includes a digital-to-analog converter configured to generate a reference signal. Further, the system includes an amplifier configured to amplify an error signal that includes a difference between the analog input signal and the reference signal. Additionally, the system includes a level-crossing based sampling circuit that includes a first comparator configured to compare the error signal with respect to a first reference level, and a second comparator configured to compare the error signal with respect to a second reference level, thereby generating event-based reset signals corresponding to a plurality of sampling instances in order to reset the digital-to-analog converter. Yet further, the system includes a trigger circuit configured to generate reset signals asynchronous to the event-based reset signals.

A method for digital-to-analog signal conversion with distributed reconstructive filtering includes receiving a digital code synchronous to a clock signal having a first frequency, determining next states of a plurality of digital-to-analog current elements based on the digital code, combining a plurality of currents to generate an output current, and generating the plurality of currents. Each of the plurality of currents is based on a corresponding control signal of a plurality of control signals. The method includes generating the plurality of control signals based on the next states of the plurality of digital-to-analog current elements. Each of the plurality of control signals selects a first voltage level, a second voltage level, or a transitioning voltage level for use by a corresponding digital-to-analog current element. The transitioning voltage level linearly transitions from the first voltage level to the second voltage level over a predetermined number of periods of the clock signal.