An analog-to-digital converter (ADC) includes an input circuit configured to receive a first analog signal output from a first sensor or a second analog signal output from a second sensor according to an operation mode and a bit stream; a filter configured to filter an output signal from the input circuit; a quantization circuit configured to generate the bit stream from an output signal of the filter; and a digital circuit configured to generate a first digital signal corresponding to the first analog signal or a second digital signal corresponding to the second analog signal by filtering the bit stream, wherein the operation mode includes a first mode selecting the first sensor and a second mode selecting the second sensor, and wherein the digital circuit refers to the second digital signal generated during the second mode to generate the first digital signal during the first mode.

A switching circuit for checking an analog input circuit of an A/D converter is shown. The switching circuit comprises the analog circuit and a comparator circuit. The analog input circuit is configured to generate a first derived signal S1 and a second derived signal S2 from an analog input signal SE of the analog input circuit. The first derived signal S1 and the second derived signal S2 are input signals for the comparator circuit, but only the first derived signal S1 is an input signal for the A/D converter. The comparator circuit is configured to check whether a deviation of the derived signals S1, S2 from each other lies within a tolerance range TOL and to output an output signal SA depending on the check, which may be further evaluated.

An analog-to-digital converter for converting a pixel signal generated from sensed light into a digital signal includes a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal, the delay circuit including a plurality of delay elements configured to generate a second signal by delaying the first signal by a first time period; and a compensator circuit configured to measure a period of the comparison signal to output a delay select signal to the delay circuit based on the measured period, the delay select signal delaying the first signal by the first time period, wherein the first time period is obtained by dividing the period of the comparison signal.

The present disclosure relates to optical phase modulation devices. The optical phase modulation devices may include a heater resistance which induces a phase change and control systems and methods of controlling the induced phase change.

The disclosed systems, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a signal encoder configured to encode a plurality of received analog signals into a single encoded analog composite signal, in accordance with a variable leading bit orthogonal coding scheme, an analog-to-digital converter (ADC) configured to convert the single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals, a synchronization module configured to provide the variable leading bit orthogonal coding scheme to the signal encoder, and a signal decoder configured to decode the single encoded digital composite signal in accordance with the variable leading bit orthogonal coding scheme, to output a plurality of digital signals containing the desired information content of the received plurality of analog signals.

An analog-to-digital converter for converting a pixel signal generated from sensed light into a digital signal includes a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal, the delay circuit including a plurality of delay elements configured to generate a second signal by delaying the first signal by a first time period; and a compensator circuit configured to measure a period of the comparison signal to output a delay select signal to the delay circuit based on the measured period, the delay select signal delaying the first signal by the first time period, wherein the first time period is obtained by dividing the period of the comparison signal.

Embodiments of this application provide example interface circuits, example electronic devices, and example data transmission apparatuses. One example interface circuit includes an interface indication end and a data transmission end. The interface circuit performs data transmission with a first device by using the data transmission apparatus. The interface circuit includes the interface indication end and the data transmission end. The interface circuit obtains indication information from an indicator of the data transmission apparatus through the interface indication end. The indication information indicates a data transmission interface protocol of the first device. The interface circuit is configured to transmit data to the first device through the data transmission end based on the data transmission interface protocol of the first device indicated by the indication information.

An apparatus includes analog-to-digital conversion (ADC) circuitry, digital processing logic, and digital-to-analog conversion (DAC) circuitry. The ADC circuitry is coupled to digitize multiple analog input signals so as to generate digital samples. The digital processing logic is configured to extract, from the digital samples, one or more first digital signals corresponding to a first selected subset of the analog input signals, and one or more second digital signals corresponding to a second selected subset of the analog input signals. The digital processing logic is further configured to output the one or more first digital signals to a digital medical instrument. The DAC circuitry is coupled to convert the one or more second digital signal into one or more analog output signals, and to output the one or more analog output signals to an analog medical instrument.

An example analog signal multiplexer includes two differential input signal ports for receiving a first and a second differential input signals, IN1 and IN2. The multiplexer further includes a differential output signal port with two output terminals OUT+ and OUT, for outputting a signal based on one or more of the input signals IN1 and IN2. Furthermore, the multiplexer includes a pair of load elements, and an additional differential output signal port that has two output terminals TERM+ and TERM. The load elements are not coupled directly to the output terminals OUT+ and OUT, but, rather, are coupled to the output terminals of the additional output signal port, TERM+ and TERM, enabling a modular approach where multiple instances of the multiplexer may be combined on an as-needed basis to realize multiplexing between a larger number of differential inputs that a single multiplexer would allow.

An electronic device for compressing sampled data comprises a memory element and a processing element. The memory element is configured to store sampled data points and sampled times. The processing element is in electronic communication with the memory element and is configured to receive a plurality of sampled data points, a slope for each sampled data point in succession, the slope being a value of a change between the sampled data point and its successive sampled data point, and store the sampled data point in the memory element when the slope changes in value from a previous sampled data point.