Methods and apparatus for dynamically controlling a quantum computer are described wherein the method includes selecting a first and second digital pulse signal stored in a memory, the first digital pulse signal having a first pulse shape and a first sample rate and the second digital pulse signal having a second pulse shape and a second sample rate, at least the first or the second sample rate being lower than an output sampling rate of a digital-to-analog converter (DAC); forming a digital pulse sequence signal, the forming including applying a first interpolation algorithm to determine a first upsampled digital pulse signal based on the first digital signal and a second interpolation algorithm to determine a second upsampled digital pulse signal based on the second digital signal, the sample rates of the first and second upsampled digital signals matching the sample rate of the DAC; and, providing the digital pulse sequence signal comprising the first and second upsampled digital pulse signals to an input of the DAC to transform the first and second upsampled digital signals into an analog pulse sequence signal for controlling the quantum device.

In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency f.sub.S, that is, at a clock-pulse period T.sub.S=1/f.sub.S, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency f.sub.D, that is, at a clock-pulse period T.sub.D=1/f.sub.D, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD.

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein Nis a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1(1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

A unity-gain buffer circuit structure, used to receive an input voltage and output an output voltage, includes a first operational amplifier and a second operational amplifier. The first operational amplifier includes a first positive input, a first output and a first negative input. The second operational amplifier, coupled electrically with the first operational amplifier, includes a second positive input, a second output and a second negative input. The second positive input is used to receive the output voltage. The second output, coupled with first negative input, is used to output a second output voltage. The second negative input, coupled with the second output, is used to receive the second output voltage. After the first negative input receives the second output voltage, an offset voltage between the output voltage outputted from the first operational amplifier and the input voltage received by the first operational amplifier is close to 0.

A method for digital-to-analog signal conversion with distributed reconstructive filtering includes receiving a digital code synchronous to a clock signal having a first frequency, determining next states of a plurality of digital-to-analog current elements based on the digital code, combining a plurality of currents to generate an output current, and generating the plurality of currents. Each of the plurality of currents is based on a corresponding control signal of a plurality of control signals. The method includes generating the plurality of control signals based on the next states of the plurality of digital-to-analog current elements. Each of the plurality of control signals selects a first voltage level, a second voltage level, or a transitioning voltage level for use by a corresponding digital-to-analog current element. The transitioning voltage level linearly transitions from the first voltage level to the second voltage level over a predetermined number of periods of the clock signal.

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

A digital-to-analog converter (DAC) for converting a digital input word to an analog output signal includes a string DAC, a first interpolator and a second interpolator. The string DAC outputs a first voltage and a second voltage in response to M most significant bits of the digital input word. The first interpolator interpolates between the first and second voltages in response to middle Q least significant bits of the digital input word and provides a first interpolated voltage. The second interpolator interpolates between the first interpolated voltage and the second voltage in response to lower P least significant bits of the digital input word.

The disclosure provides a digital-to-analog conversion device and an operation method thereof. The digital-to-analog conversion device includes a digital-to-analog conversion circuit and a slew rate enhancement circuit. The digital-to-analog conversion circuit is configured to convert a digital code into an analog voltage. An output terminal of the digital-to-analog conversion circuit outputs the analog voltage to a load circuit. A control terminal of the slew rate enhancement circuit is coupled to the digital-to-analog conversion circuit to receive a control voltage following the analog voltage. The slew rate enhancement circuit is coupled to the output terminal of the digital-to-analog conversion circuit. The slew rate enhancement circuit enhances the slew rate at the output terminal of the digital-to-analog conversion circuit based on the control voltage.

A DAC cell includes first and second transistors, drain-source coupled at a first node, a gate of the second transistor coupled to a data input (D), and third and fourth transistors, drain-source coupled at a second node, a gate of the fourth transistor coupled to a complement of the data input (DB). The circuit further includes first and second shadow transistors each coupled between the first node and ground, a gate of the first shadow transistor coupled to a switching input (S) and a gate of the second shadow transistor coupled to a complement of the switching input (SB). The circuit still further includes third and fourth shadow transistors each coupled between the second node and ground, a gate of the third shadow transistor coupled to S and a gate of the fourth shadow transistor coupled to SB.

A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform.