A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.

A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.

An analog digital converter that does not require a dedicated reference voltage, can digitize a rail-rail input signal and provide house-keeping functions to a ROIC or other IC. The RHADR system may operate without support from a main electronics board, which would only have to supply a power supply voltage to, and read the outputs from, the chip. This is achieved with (1) a Pivoting Successive Approximation Register ADC (PSAR ADC) and (2) radiation hard by design (RHBD) techniques.

A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

A digital-to-analog conversion, including: converting signal Y using word X=M+a.sup.−aN having length Ψ=α+β digits, where M is high order digits of a long control word X, a.sup.−aN is low order digits of β long control word X, wherein α≈β; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z.sub.1 is proportional to Mα long high order digits of X, and to reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in the second and third conversions, signals Z.sub.2 and Z.sub.3 are proportional to Nβ long low order digits of X and to signals Y.sub.1 and Y.sub.2, respectively, where Z.sub.2=Y.sub.1×N, and Z.sub.3=Y.sub.2×N, wherein, before the conversions, a.sup.−aN low order digits of X are multiplied by a.sup.a; and adding Z.sub.1, Z.sub.2, Z.sub.3 to generate output signal Z.sub.0, wherein Y.sub.1 and Y.sub.2 relate by Y.sub.2=Y.sub.1(1±a.sup.−a), wherein a is the base of the numbering system, α is the number of digits, by which a.sup.−aN is shifted.

A digital-to-analog conversion, including: converting signal Y using word X=M+a.sup.−aN having length Ψ=α+β digits, where M is high order digits of a long control word X, a.sup.−aN is low order digits of β long control word X, wherein α≈β; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z.sub.1 is proportional to Mα long high order digits of X, and to reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in the second and third conversions, signals Z.sub.2 and Z.sub.3 are proportional to Nβ long low order digits of X and to signals Y.sub.1 and Y.sub.2, respectively, where Z.sub.2=Y.sub.1×N, and Z.sub.3=Y.sub.2×N, wherein, before the conversions, a.sup.−aN low order digits of X are multiplied by a.sup.a; and adding Z.sub.1, Z.sub.2, Z.sub.3 to generate output signal Z.sub.0, wherein Y.sub.1 and Y.sub.2 relate by Y.sub.2=Y.sub.1(1±a.sup.−a), wherein a is the base of the numbering system, α is the number of digits, by which a.sup.−aN is shifted.

A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, R.sub.MSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.