A solid state imaging element according to an embodiment includes: a converter (14) that converts an analog pixel signal read out from a pixel into a bit value, successively for each of a plurality of bits, on the basis of a threshold voltage set according to a conversion history of the bit converted before a target bit; a plurality of voltage generation units (102a and 102b) that each generate a plurality of reference voltages; and a setting unit (12d) that sets the threshold voltage using the reference voltage selected from the reference voltages generated by each of the voltage generation units on the basis of a conversion result.

Clock alignment circuitry may include phase detection circuitry and programmable delay circuitry to facilitate aligning a data signal with a particular state of a clock signal. For example, phase detection circuitry may be disposed at a location of interest to monitor the relative timing of the clock signal and the data signal. Based on the monitored states, the programmable delay circuitry may determine the delay to be applied to the data signal (e.g., prior to propagating through logic operations and transmission to the location of interest) such that the data signal later arrives at the location of interest at a suitable time. Effectively, a programmable delay is added to the delay encountered by the data signal during processing and transmission to the location of interest such that the total delay results in the data signal arriving at the location of interest while the clock signal is in the desired state.

The disclosure describes an implementation of a combinational thermometric-R2R that includes a thermometric DAC circuit to output the coarse output steps, an R2R circuit to control the fine output steps, and a resistor in series with the thermometric and R2R circuits. The techniques of this disclosure implement a fine resolution DAC, on the order of two nanoamps per bit, that operates at low current, yet maintains monotonicity throughout the DAC output range.

The disclosure describes an implementation of a combinational thermometric-R2R that includes a thermometric DAC circuit to output the coarse output steps, an R2R circuit to control the fine output steps, and a resistor in series with the thermometric and R2R circuits. The techniques of this disclosure implement a fine resolution DAC, on the order of two nanoamps per bit, that operates at low current, yet maintains monotonicity throughout the DAC output range.

A semiconductor device includes a digital-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-analog converter to test the digital-analog converter. The test circuit includes: a charge information holding circuit that holds, as differential charge information, a difference value between a first charge according to a first current and a second charge according to a second current by at least one or more current cells among the plurality of current cells; a reference voltage generation circuit that generates a reference voltage to be comparative object; and a comparison circuit that compares a determination voltage according to the differential charge information and the reference voltage to output a comparison result.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1 (1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1 (1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.