Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

A receiver receives a signal including an interleaved symbol stream. The receiver includes a convolutional deinterleaver including a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector inputs the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

A communication control apparatus, a radio communication apparatus, a communication control method, a radio communication method, and a program capable of contributing to improving a radio communication technology related to IDMA. The communication control apparatus including: a communication unit configured to communicate with a radio communication apparatus of a radio communication system using interleave division multiple access (IDMA); and a control unit configured to allocate an interleaver type of an interleaver to be used for IDMA by the radio communication apparatus.

A time de-interleaving circuit applied to a communication system to de-interleave an interleaved signal is provided. The interleaved signal includes a plurality of cells. The time de-interleaving circuit includes a memory module and a buffering memory module. The memory module stores the cells, which are in a unit of a plurality of cells to form a plurality of cell groups. The memory module is accessed in a unit of one cell group. The buffering memory module buffers a part of the cells from the memory module to arrange an output sequence of the cells.

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

In an aspect, a method of encoding data for transmission includes reading, for a block of encoded data on which interleaving and rate-matching is to be performed, the block of encoded data from a buffer, by first and second interleaving and rate matching engines operating in parallel and, starting at first and second starting points of the buffer, respectively. Encoded output data includes the interleaved and rate matched data from both engines. In another aspect, a method of decoding received data includes reading data of a log likelihood ratio (LLR) buffer, by first and second de-interleaving and de-rate matching engines, starting at first and second starting points of the LLR buffer, respectively. Decoded output data includes de-interleaved and de-rate matched data of both engines.

A time de-interleaving circuit is located at a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. The time de-interleaving circuit includes: a data unit access address generator, generating a plurality of data unit access addresses according to a first address sequence to accordingly access the plurality of data units in a memory; and a common unit access address generator, generating a plurality of common unit access addresses according to a second address sequence to accordingly access the plurality of common units in the memory. The second address sequence is a reverse sequence of the first address sequence.

A de-interleaving circuit that performs a time de-interleaving process on an interleaved block of an interleave signal includes: an input buffer, buffering multiple information units included in a time interleaved block; a writing address generator, generating multiple writing addresses according to a predetermined rule to write the information units buffered in the input buffer to a memory; a reading address generator, generating multiple reading addresses according to the predetermined rule to read the information units from the memory; and an output buffer, buffering the information units read from the memory. The information units are stored in multiple tiles of the memory. The tiles correspond to multiple regions of the time interleaved block, the multiple regions include a first region and a second region, and the dimensions of each tile in the first region are different from the dimensions of each tile in the second region.

Proposed is a bit-interleaver for an optical line terminal of an optical access network. The bit-interleaver contains a memory reader, that provides data streams at bit level to a space-time switch. The space-time switch reads within one input cycle up to N bit sets from the data streams. The switch switches within one writing cycle up to N bits onto up to its output ports, which provide respective output vectors. A number of N OR-function elements determine within the writing cycle respective single output bits. A number of N memory elements write within the one writing cycle a respective one of the output bits into a respective one of their bit sub-elements. A control unit that controls the reading of the data streams and also the switching of the bits by the switch. The control unit controls a choice of the writing addresses.

A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.