A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

This disclosure describes techniques for performing computational operations on input unary bit streams using one or more scaling networks. In some examples, a device is configured to perform a digital computational operation, where the device includes a plurality of input wires and a plurality of output wires. Each input wire is configured to receive a respective input bit of an encoded input value, and each output wire is configured to output a respective output bit of an encoded output value. The device also includes scaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires. The device can also include hybrid binary/unary computations.

According to one embodiment of the present specification, a method for transmitting security data is disclosed. The method for transmitting security data can comprise the steps of: outputting a first sequence by scrambling a bit stream of dummy data; outputting a second sequence by scrambling the security data to be transmitted by using the bit stream; and transmitting a first code word and a second code word obtained by encoding the first sequence and the second sequence.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

A method includes receiving a DSN access request, identifying a DSN address of the DSN access request, identifying one or more DS processing units affiliated with the DSN address. The method further includes determining, for each of the one or more DS processing units, an availability level and a priority level. The method further includes selecting one DS processing unit of the one or more DS processing units based on one or more of the availability level and the priority level and forwarding the DSN access request to the selected DS processing unit. The method further includes accessing an affinity table based on the DSN address to identify the one or more DS processing units associated with an DSN address range that includes the DSN address.

A method includes receiving an DSN access request, identifying an DSN address of the DSN access request, identifying one or more DS processing units affiliated with the DSN address. The method further includes selecting a DS processing unit of the one or more DS processing units based on DS processing attributes, determining if the selected DS processing unit is associated with a favorable availability level and, when it is determined that a favorable availability level does not exist, deterministically selecting another of the one or more DS processing units and, when it is determined that a favorable availability level does exist, forwarding the DSN access request to the selected DS processing unit to be processed for storage in one or more DSN storage units.

A method includes dispersed storage error encoding a data object in accordance with temporary parameters. The method further includes generating a first source name. The method further includes sending, in accordance with the first source name, the first sets of encoded data slices to a first set of storage units for temporary storage therein. When a determination is made to permanently store the data object, the method further includes recovering the data object from the first sets of encoded data slices. The method further includes dispersed storage error encoding the recovered data object in accordance with permanent parameters to produce second sets of encoded data slices. The method further includes generating a second source name. The method further includes sending, in accordance with the second source name, the second sets of encoded data slices to a second set of storage units for permanent storage therein.