Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems.

Techniques are described herein to terminate a list decoding operation before its completion based on performing one or more error check processes. A transmitted codeword encoded using a polar code may include one or more error check vectors interspersed with one or more information vectors. Upon receiving the codeword, a decoder may perform a list decoding operation on the received codeword. Upon decoding one of the error check vectors, the decoder may determine whether at least one candidate path used in the successive cancellation list decoding operation passes an error check process based on the error check vector. If no candidate paths satisfy the error check process, the decoder may terminate the list decoding operation. In some examples, the decoder may recheck whether candidate paths satisfy the error check operation at intermediate positions between error check vectors. Such rechecking may occur while decoding information vectors.

A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.

An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.

A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector α.sub.v.sup.(l) of soft information from a parent node; computing a vector α.sub.v.sub.l.sup.(l) of soft information for a left child of node v; providing node v with a vector β.sub.v.sub.l.sup.(l) of hard decisions from the left child and using it with α.sub.v.sup.(l) to create a soft information vector α.sub.v.sub.r.sup.(l) and passing it to a right child of node v; providing node v with a vector β.sub.v.sub.r.sup.(l) of hard decisions from its right child and using it with β.sub.v.sub.l.sup.(l) to create a hard decision vector, β.sub.v of hard decisions, and passing it to its parent node; updating, when v is a i.sup.th leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.

Decoders are provided for memory systems. A decoder includes a seed generator that generates seeds based on a physical address corresponding to a read request from a host; a descrambling module that receives a sequence from a storage area among, multiple storage areas, corresponding to the physical address, and descrambles the sequence using the seeds to generate multiple descrambled sequences; and a selector that selects one of descrambled sequences based on syndrome weight values of the descrambled sequences.

A decoder can receive an indication that a portion of a codeword has been decoded during a decoding operation. The decoder can determine a group of candidate output values of the decoding operation for the portion of the codeword, and eliminate one or more candidate output values from the group of candidate output values based on a decoded check code for each of the group of candidate output values. In response to determining that all of the candidate output values have been eliminated from the group of candidate output values, the decoder can terminate the decoding operation.

A successive cancellation list-based decoder and a decoding method thereof are provided. In the method, an error check is performed on a set of data bits. A data unit includes the set of the data bits and at least one first check bit. Part of the set of data bits are considered as at least one second check bit. At each of the second check bits, its previous error-check result are verified, where the verified result is related to a comparison between each of the previous first check bits and a value obtained through a function calculation on corresponding data bits. The verified result at each of the second check bits determines whether to continue decoding of the set of data bits or to early terminate the decoding process. The method is able to increase the probability for early termination of the decoding process and to improve the decoding efficiency.

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, flash memory cells are arranged along word lines to which read voltages are applied to sense programmed states of the memory cells, with the flash memory cells along each word line being configured to concurrently store multiple pages of data. An encoder circuit is configured to apply error correction encoding to input data to form code words having user data bits and code bits, where an integral number of the code words are written to each page. A reference voltage calibration circuit is configured to randomly select a single selected code word from each page and to use the code bits from the single selected code word to generate a set of calibrated read voltages for the associated page.

A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector .sub.v.sup.(l) of soft information from a parent node; computing a vector .sub.v.sub.l.sup.(l) of soft information for a left child of node v; providing node v with a vector .sub.v.sub.l.sup.(l) of hard decisions from the left child and using it with .sub.v.sup.(l) to create a soft information vector .sub.v.sub.r.sup.(l) and passing it to a right child of node v; providing node v with a vector .sub.v.sub.r.sup.(l) of hard decisions from its right child and using it with .sub.v.sub.l.sup.(l) to create a hard decision vector, .sub.v of hard decisions, and passing it to its parent node; updating, when v is a i.sup.th leaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.