A storage system includes a first information processor, a second information processor, and a superordinate device. The first information processor includes a first memory device that stores therein the data, a difference generator that generates difference data representing a difference between updating data received from the superordinate device and the data stored in the first memory device before updating, a second memory device stores therein the generated difference data, and a data transmitter that transmits the stored difference data to the second information processor. The second information processor includes a third memory device that stores therein the parity, a data receiver that receives the difference data transmitted from the data transmitter, and a parity difference applier that generates a post-updating parity that is to be written into the third memory device by applying the received difference data to the stored parity before the updating.

An encoder that supports multiple code rates and code lengths is disclosed. A shift register utilized by the encoder may be scaled in size based on a selected code rate or code length. The shift register shifts a bit series for the matrix without requiring fixed feedback points within the register. The sizes of the matrix and bit series are based on the selected code rate or code length, and the encoder loads the bit series into a first portion of the shift register, and a division of the bit series into a second portion of the shift register located adjacent to the first portion. The encoder periodically repopulates the shift register from memory to simulate circular shifting of the bit series without feedback points. Accordingly, complexity of the encoder is reduced.

A writing circuit for writing write data into a memory comprises an evaluator configured for providing an error handling code on the basis of the write data. A modifier reversibly modifies extended write data comprising both the write data and the error handling code in dependence on address information related to a writing address in order to provide modified extended write data. A writer writes the modified extended write data in a position of the memory defined by a writing address. A reading circuit for reading extended read data from a memory comprises a reader configured for reading the extended read data from a position of the memory defined by a reading address. A de-modifier modifies the extended read data in dependence on address information related to a reading address in order to provide extracted read data and an extracted error handling code. An error-detector detects based on the extracted error handling code whether the extracted read data comprises an error.

Methods and encoders for encoding information bits to generate codewords for transmission across a communication channel are described. The method includes receiving input data comprising bits of information bits and frozen bits. Each bit has a value. Further, the method identifies at least one special arrangement in a subset of input data depending on locations of the information bits and the frozen bits. This subset of input data is of length L. The subset of input data has at least one special arrangement that enables direct computations instead of a series of computations to determine a preliminary output. The method generates a codeword for the input data from the preliminary output.

Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

A non-systematic convolutional decoder of a convolutionally encoded multi-level data stream includes a shift register and two or more paths of exclusive-OR (XOR) gates, arranged to reconstruct an original input information stream, each path having a quantiser arranged to quantise the signal to two levels, and a set of XOR gates arranged to match an encoding path in an associated convolutional encoder, and a selector arranged to feed an output from each path to a single input of the shift register. If the paths have differing values at their output, the selector may choose the value from the path based upon a function of the multi-level signals associated with each path, such as the path with the largest absolute signal level. The decoder provides a simple means for decoding signals while allowing the signal to also or instead be decoded using e.g. a Viterbi decoder if higher performance is required.

A method for data communication between a first node and a second node over a data path includes determining one or more redundancy messages from data messages at the first node using an error correcting code and transmitting messages from the first node to the second node. The transmitted messages include the data messages and the redundancy messages. The method includes, receiving, at the first node, a first plurality of messages including messages indicative of a rate of arrival at the second node of the messages transmitted from the first node and messages indicative of successful and unsuccessful delivery of the messages transmitted from the first node to the second node. A first transmission limit and a second transmission limit are maintained according to the first plurality of messages. Transmission of messages from the first node to the second node is limited according to the maintained first transmission limit, and according to the second transmission limit.

A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.

A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.