m r-Ary trees for generating High-Rate MSR (HMSR) erasure codes for application in data storage systems. Nodes in the tree structures represent systematic and parity storage nodes. Each parity symbol for the HMSR erasure codes will be a linear combination of maximum k+k/r systematic symbols. The tree structures show that when a systematic node fails, its original systematic symbols can be recovered by accessing symbols for each of its leaf nodes from each of the remaining nodes. Traversing the m r-Ary trees to design a codeword array will provide the linear equations needed to solve for and recover the lost systematic symbols. When forming the linear equations, random number or other coefficients can be added to the systematic symbols to construct the parity symbols. The parities of the HMSR erasure code will ensure recovery of any systematic node failure using significantly reduced IO and network bandwidth.

The present subject-matter relates to transmitting a real-time data stream, namely simultaneously to multiple receivers over unreliable networks (e.g. wireless multicast), in a timely and reliable manner, in particular to a method, apparatus and computer program product for feedback-based real-time network coding. It is disclosed a computer-implemented method for a transmitting node, a receiving node, and an intermediate node of feedback-based real-time network coding from a transmitter and to one or more receivers, in particular comprising a linear combination of packets from the transmitter; determining whether the received linear combination of packets is linearly independent of previous linear combinations of packets; determining the validity of a priority level of the packets; determining validity of the deadline of the packets; determining whether a packet is to be removed from a transmit queue, and if determined removing it. There are also disclosed said transmitting, receiving, and intermediate nodes.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a chiplet-based multi-chip module (MCM) is disclosed. The chiplet-based MCM includes a first integrated circuit (IC) chiplet comprising a first interface to receive a first set of information-carrying signals associated with a memory access operation. Conversion circuitry generates a second set of support signals associated with the memory access operation. The conversion circuitry aggregates the second set of support signals with the first set of information-carrying signals to generate an aggregate set of signals associated with the memory access operation. A second interface transmits the aggregate set of signals. Memory, comprising a memory interface coupled to the second interface of the first IC chiplet receives the aggregate set of signals.

Provided is an apparatus for designing a quantum code, which includes an analyzing unit for analyzing at least one quantum error generated in a quantum error channel as at least one binary error by using a standard form codeword stabilized quantum (CWS) code, a code generating unit for generating a binary error-correcting code which corrects the at least one binary error, a word operator generating unit for generating at least one word operator of the CWS code by using the at least one binary error-correcting code, and a codeword generating unit for generating at least one codeword including at least one entangled qubit (ebit) by using the at least one word operator.

A multi-chip module (MCM) includes a first integrated circuit (IC) chip including a first interface defining a first number of interface contacts. Conversion circuitry receives a first set of information-carrying signals associated with a memory access operation. Conversion circuitry generates a second set of non-information-carrying signals associated with the memory access operation and aggregates the second set of non-information-carrying signals with the first set of information-carrying signals to generate an aggregate set of signals. A second interface transmits the aggregate set of signals. Memory, including a memory interface coupled to the second interface of the first IC chiplet, receives the aggregate set of signals.