A first signal generated from a signal generator may be synchronized with a local clock of a first device at a first time, and sent to a second device, the first signal having a first frequency. A second signal generated from the signal generator may be further synchronized with the local clock of the first device at a second time, the second signal having a second frequency different from the first frequency, and a difference between the second time and the first time being within a predetermined range of a predetermined time difference. The second signal may then be sent to the second device to enable the second device to determine a distance between the first device and the second device based at least in part on a phase difference between the first signal and the second signal.

A first signal generated from a signal generator may be synchronized with a local clock of a first device at a first time, and sent to a second device, the first signal having a first frequency. A second signal generated from the signal generator may be further synchronized with the local clock of the first device at a second time, the second signal having a second frequency different from the first frequency, and a difference between the second time and the first time being within a predetermined range of a predetermined time difference. The second signal may then be sent to the second device to enable the second device to determine a distance between the first device and the second device based at least in part on a phase difference between the first signal and the second signal.

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.

An example system comprising a first transceiver configured to receive a request airframe from a second transceiver over a wireless link, the request airframe including a first time indication indicating a first time TS1, a second time indication indicating a second time TS2 that the request airframe was received, generate a respond airframe and including a third time indication indicating a third time TS3 that the respond airframe is transmitted to the second transceiver, transmit the respond airframe to the second transceiver, provide a timestamp information request to second transceiver, receive a timestamp information response, the timestamp information response including a fourth time indication indicating a fourth time TS4, calculate a counter offset using the first time, second time, third time and fourth time as follows:

[00001]$\mathrm{counter}\mathrm{offset}=\frac{\left(\mathrm{TS}1+\mathrm{TS}4-\mathrm{TS}3-\mathrm{TS}2\right)}{2},$

calculate a phase offset based on the counter offset, and correct a phase of the first transceiver.

An example system comprising a first transceiver configured to receive a request airframe from a second transceiver over a wireless link, the request airframe including a first time indication indicating a first time TS1, a second time indication indicating a second time TS2 that the request airframe was received, generate a respond airframe and including a third time indication indicating a third time TS3 that the respond airframe is transmitted to the second transceiver, transmit the respond airframe to the second transceiver, provide a timestamp information request to second transceiver, receive a timestamp information response, the timestamp information response including a fourth time indication indicating a fourth time TS4, calculate a counter offset using the first time, second time, third time and fourth time as follows:

[00001]$\mathrm{counter}\mathrm{offset}=\frac{\left(\mathrm{TS}1+\mathrm{TS}4-\mathrm{TS}3-\mathrm{TS}2\right)}{2},$

calculate a phase offset based on the counter offset, and correct a phase of the first transceiver.

A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

A method for initial timing synchronization for a WTRU to communicate with a network includes receiving an in-channel narrowband synchronization sequence from the network to enable initial coarse timing synchronization, determining coarse timing offset and a range between a beam source of a network transmitter and the WTRU, selecting a wideband sequence for fine timing synchronization using the estimated range, transmitting the selected wideband sequence for fine timing synchronization during an uplink timing occasion, receiving from the network a transmission of the selected wideband sequence for fine timing synchronization, and establishing fine timing synchronization between the WTRU and the network using the selected sequence.

Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.