Methods of guaranteed reception and of processing of a digital signal in an avionics system comprise a plurality of computers, each computer comprising processing electronics and a software layer, which, on receipt of an event, carries out the following steps: at a first instant, sending to each of the other computers of a first signal (ACK) of reception of the event; at a second instant termed TimeOut ACK, if the electronic computer has not received one of the first signals emanating from one of the other computers, sending of a second failure signal (FAIL) to each of the other computers; at a third instant termed TimeOut GARANTEED, if a second failure signal has been received by the computer, absence of taking into account of the event by the computer and if no failure signal has been received by the computer, taking into account of the event by the data processing electronics of the computer.

A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.

A timing lock identification method is provided according to an embodiment of the disclosure. The method includes: generating one or more first phase adjustment pulses and one or more second phase adjustment pulses by a timing recovery circuit, where the one or more first phase adjustment pulses are configured to increase a phase of an output signal of an oscillator, and the one or more second phase adjustment pulses are configured to decrease the phase of the output signal; and obtaining a difference value between the number of the one or more first phase adjustment pulses and the number of the one or more second phase adjustment pulses in a detection window and determining whether the timing recovery circuit reaches a locking state of timing recovery according to the difference value. Furthermore, a signal receiving circuit is provided according to an embodiment of the disclosure.

An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.

A method and device for transmitting data reliably to at least one item of equipment is provided, wherein: from its initial clock H.sub.1, an item of equipment generates at least one first clock H.sub.1U from a rising edge of the initial clock H.sub.1 with a frequency F.sub.1U and a second clock H.sub.1D from a falling edge of the initial clock H.sub.1, with a frequency F.sub.1D, the item of equipment: reads the received data using at least one first rising edge of H.sub.1U and one falling edge consecutive to the first rising edge of H.sub.1U, then reads the received data using a first rising edge of H.sub.1D and a falling edge consecutive to the first rising edge of H.sub.1D, the four clock edges used being consecutive by 2F.sub.1, decodes at least the four messages using an error-correcting code, when at least one decoded message is correct, it uses the information contained in this message to drive a device linked to said item of equipment.

A method of frame synchronization comprises receiving a stream of bits, the stream comprising a sequence of frames, wherein each frame comprises a frame counter value representing the number of the frame in the sequence, and frame check bits for checking the validity of the frame counter value. The method comprises decoding a first section of bits, and trailing a first portion of the first section of bits as a trial counter value, and a second portion of the first section of bits as trial check bits. The method comprises checking if the trial counter value corresponds to a valid frame counter value using the trial check bits, and synchronizing based on whether the trial counter value is determined to correspond to a valid frame counter value.

A multiple access scheme is provided. A first communications terminal encodes a first data stream using a forward error correction (FEC) code, and scrambles the encoded first data stream based on a first scrambling signature. A second communications terminal encodes a second data stream using the FEC code, and scrambles the encoded second data stream based on a second scrambling signature. The first scrambling signature and the second scrambling signature are used, respectively, by the first terminal and the second terminal to distinguish the first encoded data stream from the second encoded data stream as respectively originating from the first terminal and the second terminal in a multiple access scheme, whereby the first encoded data stream and the second encoded data stream simultaneously share a wireless communications channel. The FEC code is a low density parity check (LDPC) code configured with a data node degree of two or three.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

The invention provides a communications device which uses a clock circuit for generating a clock signal, the clock circuit comprising a tuneable oscillator. The clock frequency is varied to make sure it remains within a tolerance range, so that the device can continue to receive messages correctly. An error rate of received messages is determined, and in response to the error rate exceeding a threshold, a setting of the resistor arrangement and/or the capacitor arrangement is changed to change the clock signal frequency thereby to lower the error rate.

A communication device includes a receiver configured to receive a signal, a sampler configured to sample the signal for each digital value of the predefined sequence of digital values in the signal, a memory configured to store a table giving, for each of a plurality of combinations of one or more preceding first digital values and a following second digital value, a threshold for a signal level to detect the second digital value, an initializer configured to, for a combination in a subset of the plurality of combinations, initialize the table based on a sample of the signal for the second value, and for a combination outside of the subset, select a combination from the subset and initialize the table based on a sample of the signal for the second value of the selected combination.