Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

A receiver generates a stream of digital samples from an analog electrical signal that represents data conveyed to the receiver over a communication channel, where the stream of digital samples comprises current samples corresponding to a current timepoint, previous samples corresponding to a timepoint earlier than the current timepoint, and subsequent samples corresponding to a timepoint later than the current timepoint. The receiver generates previous, current, and subsequent phase offset signals based on the previous, current, and subsequent samples, respectively. The receiver uses the previous phase offset signal to adjust clock frequency and clock phase of the current samples, thereby resulting in current adjusted samples. The receiver adjusts clock phase of the current adjusted samples based on any one of the previous, current, and subsequent phase offset signals. In some examples, receiver adjusts the clock phase of the current adjusted samples based on the subsequent phase offset signal.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

An electric system comprising communication link between a signal transmitting end and a signal receiving end, wherein, at the signal transmitting end, a number of data bits are integrated into a low frequency signal to form an integrated signal. Each data bit is transmitted as part of a symbol. Each symbol comprises a predefined number of bits encoding at least one data bit, the state of some of the bits of each symbol being dependent on the state of the low frequency symbol.

An electric system comprising communication link between a signal transmitting end and a signal receiving end, wherein, at the signal transmitting end, a number of data bits are integrated into a low frequency signal to form an integrated signal. Each data bit is transmitted as part of a symbol. Each symbol comprises a predefined number of bits encoding at least one data bit, the state of some of the bits of each symbol being dependent on the state of the low frequency symbol.

A random access memory (RAM) including a deserializer is disclosed. The RAM further comprises a continuous-time linear equalizer (CTLE) including a first input terminal that receives an input signal for the RAM and a first output terminal communicatively connected to the deserializer, the CTLE configured to perform a channel gain compensation on the input signal received by the first input terminal and to transmit the compensated input signal to the deserializer. The RAM may further comprise a decision feedback equalizer (DFE) including a second input terminal communicatively connected to the CTLE and a second output terminal communicatively connected to the deserializer, the DFE configured to reduce an inter-symbol interference (ISI) of the input signal.

Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.