A printed wiring board includes a laminated base material including an insulating layer and a conductor layer formed on the insulating layer, and a solder resist layer laminated on the laminated material and including photosensitive resin. The resist layer has surface portion and portion in contact with the laminated material, the conductor layer has pattern including conductor pads in contact with the resist layer such that the pads are positioned in openings in the resist layer, and the resist layer satisfies a first condition that a chemical species derived from a photopolymerization initiator has concentration higher in the portion in contact with the laminated material than concentration in the surface portion and/or a second condition that the chemical species derived from the initiator in the portion in contact with the laminated material has photopolymerization initiating ability higher than a chemical species derived from a photopolymerization initiator in the surface portion.

A method of manufacturing a printed circuit board or a sub-assembly thereof by coupling at least two elements of insulating materials with different properties on adjacent side surfaces and covering the elements with a layer of conductive material and building up at least one further layer at least partly overlapping the at least two elements.

A wire extends through a ceramic body. The wire comprises a material selected from the group consisting of platinum, palladium, rhodium, iridium, osmium and alloys of platinum, palladium, rhodium, iridium, and osmium. The wire directly contacts the ceramic body to form a substantially hermetic seal between the ceramic body and the wire.

A method of lamination of dielectric circuit materials is provided. The method includes preparing first and second circuit layers of dielectric materials, stacking the first and second circuit layers with circuit trace elements interposed between the first and second circuit layers and ultrasonically welding the second circuit layer onto the first circuit layer around the circuit trace elements.

A wafer-level manufacturing method for embedding a passive element in a glass substrate is disclosed. A highly doped silicon wafer is dry etched to form a highly doped silicon mould wafer, containing highly doped silicon passive component structures mould seated in cavity arrays; a glass wafer is anodically bonded to the highly doped silicon mould wafer in vacuum pressure to seal the cavity arrays; the bonded wafers are heated so that the glass melts and fills gaps in the cavity arrays, annealing and cooling are performed, and a reflowed wafer is formed; the upper glass substrate of the reflowed wafer is grinded and polished to expose the highly doped silicon passives; the passive component structure mould embedded in the glass substrate is fully etched; the blind holes formed in the glass substrates after the passive component structure mould has been etched is filled with copper by electroplating; the highly doped silicon substrate and unetched silicon between the cavity arrays are etched, and several glass substrates embedded with a passive element are obtained; to form electrodes for the passives, a metal adhesion layer is deposited, and a metal conductive layer is electroplated. The process is simple, costs are low, and the prepared passive elements have superior performance.

The invention relates to an aqueous alkaline pre-treatment solution for use prior to deposition of a palladium activation layer on a substrate in manufacturing an article with an integrated circuit and a method and use thereof, wherein the solution comprises: at least one hydroxycarboxylic acid or salt thereof according to the general formula (I)

[RCH.sub.2—(RCH).sub.n—COO.sup.−].sub.m M.sup.m+  (I)

wherein n is integer from 2 to 4 and m is 1 or 2, R is independently H or OH with proviso that at least one R is OH, and wherein M.sup.m+ with m: 1 is hydrogen, ammonium or alkali metal; or M.sup.m+ with m: 2 is earth alkali metal, at least one polyoxyethylene sorbitan fatty acid ester, at least one sulphonated fatty acid or a salt thereof.

A desmear module for a horizontal galvanic or wet-chemical process line for metal, in particular copper, deposition on a substrate to be treated for a removal of precipitates comprising a desmear container connectable to a desmear unit, a pump and at least a first liquid connection element for connecting said pump with the desmear unit, wherein said pump is in conjunction with said desmear unit by said at least first liquid connection element; and wherein a treatment liquid level is provided inside the desmear module, which is above an intake area of the pump; wherein the desmear module further comprises at least a first liquid area, at least an adjacent second liquid area comprising the intake area of the pump, and at least a first separating element arranged between said at least first liquid area and said at least second liquid area.

A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.

Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.

A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.