A method for step-soldering includes applying a first solder alloy having a melting point in a temperature range from 160 to 210° C. to a jointed portion of a first electronic component and a substrate, and heating them in the temperature range from 160 to 210° C., and applying a second solder alloy having the melting point in a temperature range lower than 160° C. to a joint portion of a second electronic component and the substrate, and heating them in the temperature range lower than 160° C. The first solder alloy consists of 13-22 mass % of In, 0.5-2.8 mass % of Ag, 0.5-5.0 mass % of Bi, 0.002-0.05 mass % of Ni and a balance Sn.

A separable and reconnectable connector for semiconductor devices is provided that is scalable for devices having very small contact pitch. Connectors of the present disclosure include signal pins shielded by pins electrically-coupled to ground. One or more signal pins in a contact array are electrically-shielded by at least one ground pin coupled to a ground plane. Embodiments thereby provide signal pins, either single-ended or a differential pair, usable to transmit signals with reduced noise or cross-talk and thus improved signal integrity. Embodiments further provide inner ground planes coupled to connector ground pins to shield pairs of differential signal pins without increasing the size of the connector. Inner grounding layers can be formed within isolation substrates incorporated into connector embodiments between adjacent pairs of signal pins. These buried ground layers provide additional crosstalk isolation in close proximity to signal pins, resulting in improved signal integrity in a significantly reduced space

A circuit board includes at least one circuit board unit sequentially stacked in a thickness direction of the circuit board, an insulating layer, an electromagnetic shielding layer, and a barrier layer. The circuit board unit includes a substrate layer, and two conductive layers respectively disposed on two opposite sides of the substrate layer in a thickness direction of the substrate layer, and each of the conductive layers includes a plurality of signal lines. The insulating layer is located on a side of an outermost conductive layer away from the substrate layer. The electromagnetic shielding layer is located on a side of the insulating layer away from the substrate layer. The barrier layer is located between the electromagnetic shielding layer and the outermost conductive layer. The barrier layer at least covers a plurality of signal lines in the outermost conductive layer.

Disclosed embodiments include alignment apparatuses for circuit boards, inverter assemblies, and methods for fabricating an assembly with a circuit board placed on an alignment apparatus. An illustrative apparatus includes an electrically insulative substrate having a first substantially planar surface and a second substantially planar surface forming an opposing side of the first substantially planar surface. The second substantially planar surface defines therein self-aligning features that are configured to align at least one power module pin with the electrically insulative substrate. The first substantially planar surface has at least one alignment feature configured to align a printed circuit board with the electrically insulative substrate. The apparatus also includes a routing feature coupled to the electrically insulative substrate. The routing feature is configured to route at least one low voltage conductor.

An optoelectronic apparatus (200) and an optoelectronic integration method are disclosed, so that bandwidth for signal transmission can be improved, and signal transmission performance is improved. The optoelectronic apparatus (200) includes: a printed circuit board PCB (201), where a first substrate (203) and a second substrate (205) are separately disposed on the PCB (201), an application specific integrated circuit ASIC (202) is disposed on the first substrate (203), and an optoelectronic component (204) is disposed on the second substrate (205); and a flexible printed circuit FPC (206), where a first end of the FPC (206) is disposed on an upper surface of the first substrate (203) and is electrically connected to the ASIC (202), and a second end of the FPC (206) is disposed on the second substrate (205) and is electrically connected to the optoelectronic component (204).

A first circuit board includes a positive output pin and a negative output pin of a power conversion circuit, each of which has a shape projecting from a second main surface. A second circuit board has a positive through via and a negative through via, each of which has a shape extending between a third main surface and a fourth main surface. The second main surface of the first circuit board and the third main surface of the second circuit board are physically in close contact with each other. The positive output pin is inserted through the positive through via to reach the fourth main surface. The negative output pin is inserted through the negative through via in such a manner as to reach the fourth main surface. The load receives a current supplied from the power conversion circuit through the positive output pin and the negative output pin.

The present disclosure provides an adapter board, a for manufacturing the same and a circuit board assembly. The adapter board includes a board body, a first component buried in the board body, a first connector located on a first surface of the board body and configured to be connected with a circuit board and a second component, a second connector located on a second surface of the board body and configured to be connected with a second component, a first conductive body and a second conductive body buried in the board body. One end of the first conductive body is connected with the first component. The other end of the first conductive body is connected with the first connector. One end of the second conductive body is connected with the first component. The other end of the second conductive body is connected with the second connector

Disclosed are an electronic component package, an electronic assembly, and a voltage regulation module. The electronic component package includes a substrate and a first electronic component. The substrate includes a first surface and a second surface; wherein the first surface is arranged with a first conductive layer, and the second surface is arranged with a second conductive layer. The substrate defines a first conductive hole connected to the first conductive layer and a second conductive hole connected to the second conductive layer. The first electronic component is received in the substrate and arranged with a first electrical connection terminal and a second electrical connection terminal; the first electrical connection terminal is connected to the first conductive layer through the first conductive hole, and the second electrical connection terminal is connected to the second conductive layer through the second conductive hole. The first electronic component is a passive electronic component.

Memory on Package (MOP) apparatus with reverse CAMM (Compression Attached Memory Module) and compression mount technology (CMT) connector(s). The MOP includes a first (MOP) substrate to which one or more CPUs, SoC, and XPUs that is operatively coupled to one or more CAMMs with a CMT connector(s) disposed between an array of CMT contact pads on the CAMM substrate and an array of CMT contact pad on the substrate. The one or more CAMMs are include multiple memory chips or packages such as LP DDR chips or DDR (S)DRAM chips/packages mounted to an underside of the CAMM substrate via signal coupling means such as a ball grid array (BGA), where the CAMM orientation is inverted such that the memory chips/packages are disposed downward, resulting in a reduced Z-height of the MOP. A MOP may include two CAMMs with a respective CMT connector disposed between the CAMM substrates and the MOP substrate.

A multilayer substrate includes a stacked body including a first main surface, and a conductor pattern (including a mounting electrode provided on the first main surface, and a first auxiliary pattern provided on the first main surface). The stacked body includes a plurality of insulating base material layers made of a resin as a main material and stacked on one another. The first auxiliary pattern is located adjacent to or in a vicinity of the mounting electrode. The mounting electrode, in a plan view of the first main surface (when viewed in the Z-axis direction), is interposed between a different conductor pattern (the mounting electrode) and the first auxiliary pattern.