[Object] Provided is a printed circuit board ensuring a degree of freedom in circuit design and unlikely to cause a circuit connection failure. [Solving Means] A middle interlayer circuit 11, an upper surface side interlayer circuit 12, and a lower surface side interlayer circuit 13 are formed from a connection surface-less integral conductor. In addition, a connection surface 33 between the upper surface side interlayer circuit 12 and an upper surface side surface layer circuit 14 and a connection surface 34 between the lower surface side interlayer circuit 13 and a lower surface side surface layer circuit 15 lack a connection surface in a plate thickness direction, and thus a satisfactory connection state is achieved. Accordingly, a first circuit 10 is unlikely to cause a connection failure. In addition, the upper surface side interlayer circuit 12 and the lower surface side interlayer circuit 13 can be disposed at misaligned positions in the plane direction of the printed circuit board, and thus the degree of freedom in circuit design increases. Plane circuits 24 and 16 not connected to the first circuit can be disposed with insulating layers 31 and 32 sandwiched below the upper surface side interlayer circuit 12 or above the lower surface side interlayer circuit 13.

A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate is provided with two first pads, two second pads, and two first sub-circuits. The first pads and the second pads are electrically connected to the first sub-circuits. The second substrate has a top surface, a bottom surface, a lateral edge, and two openings. The bottom surface of the second substrate is attached to the top surface of the first substrate. The openings extend from the top surface to the bottom surface of the second substrate. The first pads of the first substrate are in the opening of the second substrate; the second pads of the first substrate are not covered by the second substrate. The second substrate is further provided with a pad on the top surface and a second sub-circuit electrically connected to the pad of the second substrate.

A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.

A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

The present disclosure relates to an apparatus for manufacturing FPCB and method for manufacturing FPCB, having no limitations of length of a circuit pattern being formed on a base film.

A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate is provided with a first pad, a second pad, and a first sub-circuit. The first pad and the second pad are electrically connected to the first sub-circuit. The second substrate has a top surface, a bottom surface, and an opening. The bottom surface of the second substrate is attached to the top surface of the first substrate. The opening extends from the top surface to the bottom surface of the second substrate. The first pad of the first substrate is in the opening of the second substrate; the second pad of the first substrate is not covered by the second substrate. The second substrate further provided with a pad on the top surface and a second sub-circuit electrically connected to the pad of the second substrate.

A first conductor layer is provided on a first surface of an insulating plate, and has a first volume. A second conductor layer is provided on a second surface of the insulating plate, and has a second volume. A third conductor layer is provided on a second surface of the insulating plate, and has a second volume. The third conductor layer has a mounting region thicker than the second conductor layer. The sum of the second and third volumes is greater than or equal to 70% and smaller than or equal to 130% of the first volume. A semiconductor chip is provided on the mounting region. A sealing part is formed of an insulator, and seals the semiconductor chip within a case.

There is provided a method of fabricating a package substrate. The method may include forming an isolation trench in a conductive layer, and forming a first dielectric layer on the conductive layer to provide an isolation wall portion filling the isolation trench. The method may include recessing the conductive layer to form circuit patterns in circuit trenches defined and separated by the isolation wall portion. The method may include forming a second dielectric layer covering the circuit patterns, and patterning the first and second dielectric layers to expose portions of the circuit patterns. The exposed portions of the circuit patterns may act as connectors.

A method of making a security mesh comprises forming on a conductive substrate an alumina film having through-holes in which metal, e.g., copper, through-wires are formed. First surface wires are formed on one surface of the alumina film and second surface wires are formed on the second, opposite surface of the alumina film in order to connect selected through-wires into a continuous undulating electrical circuit embedded within the alumina film. The security mesh product comprises an alumina film having a continuous undulating electrical circuit comprising copper or other conductive metal extending therethrough. A stacked security mesh comprises two or more of the mesh products being stacked one above the other.

This transmission board production method is for producing a plurality of transmission boards from a panel having a copper foil on a surface thereof, the plurality of transmission boards each including a transmission path, the transmission board production method including: a resist formation step of forming a photoresist on the copper foil; an exposure step of irradiating the photoresist with light via a photomask; a resist removal step of removing, of the photoresist, either of a part irradiated with the light and a part not irradiated with the light; and an etching step of performing wet etching at a part, of the copper foil, exposed through the resist removal step, using an etching solution. The photomask includes a pattern for forming the transmission path included in each of the plurality of transmission boards, so that the transmission paths are along each other. The photomask is formed so that, of the copper foil, a part around each of a plurality of the transmission paths to be formed through the etching step is removed or remains such that a part where the copper foil remains and a part where the copper foil does not remain are not mixed, through the etching step. In the etching step, the etching solution moves relative to the panel along each transmission path to be formed through the etching step.