Methods for orientation and placement of computing devices are presented. Aspects include applying, using a viscous material application device, a layer of a viscous material to a surface of an object, the layer of the viscous material having a plurality of computing devices disposed therein. The layer of the viscous material is allowed to dry during a drying period, wherein each of the plurality of computing devices comprises a first material applied to a first side of each of the plurality of computing devices, the first material having a first characteristic. And each of the plurality of computing devices comprises a second material applied to a second side of each of the plurality of computing devices, the second material having a second characteristic. And each of the plurality of computing devices is configured to perform, during the drying period, a self-orientation operation.

A circuit board is obtained by providing a wiring pattern on an insulating board. The circuit board includes a first region and a second region. In the first region, a first wiring pattern is provided on which a first surface treatment is applied. In the second region, a second wiring pattern is provided on which a second surface treatment having a cutting fluid resistance and/or a humidity resistance lower than the first surface treatment is applied.

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.

A coating pattern formation method includes adjusting lyophilicity of a pattern region provided on a substrate, and forming a coating pattern having a shape of the pattern region by applying a coating liquid to the pattern region after the adjusting of the lyophilicity of the pattern region. The lyophilicity of the pattern region is adjusted such that the pattern region is divided into a plurality of small pattern regions in at least one division direction, such that adjacent small pattern regions have different lyophilicity, such that a small pattern region spaced away from an end of the pattern region has the lowest lyophilicity among the small pattern regions in the at least one division direction, and such that the lyophilicity of the small pattern regions increases from the small pattern region having the lowest lyophilicity toward the end of the pattern region.

A printed circuit board, divided into a printed circuit board area and a peripheral area surrounding the printed circuit board area, includes: a plurality of unit printed circuit boards provided in the printed circuit board area; a base portion provided in the peripheral area and the printed circuit board area, and including a circuit pattern portion and an insulating material portion; a first solder resist portion provided in the peripheral area on a first surface of the base portion and a second surface of the base portion, the first surface being opposite to the second surface; and a second solder resist portion provided in the printed circuit board area on the first surface of the base portion and the second surface of the base portion. The first solder resist portion surrounds the second solder resist portion in the printed circuit board area. The first solder resist portion includes a first filler and the second solder resist portion includes a second filler that is different from the first filler.

A wiring board manufacturing method and a wiring board in which a pattern can be simply and easily formed even when using a coating composition having a high surface tension are provided. The method includes a transferring step of bringing a resin composition containing a first compound inducing a low surface free energy and a second compound inducing a surface free energy which is higher than that of the first compound into contact with a master on which a desired surface free energy difference pattern is formed and curing the resin composition to form a base material to which the surface free energy difference pattern is transferred; and a conductor pattern forming step of applying a conductive coating composition onto a pattern transfer surface of the base material to form a conductor pattern, the base material having a pattern of a high surface free energy region and a low surface free energy region, and the high surface free energy region having a surface free energy of more than 62 mJ/m.sup.2.

Aqueous dispersions of artificially synthesized, mussel-inspired polyopamine nanoparticles were inkjet printed on flexible polyethylene terephthalate (PET) substrates. Narrow line patterns (4 m in width) of polydopamine resulted due to evaporatively driven transport (coffee ring effect). The printed patterns were metallized via a site-selective Cu electroless plating process at a controlled temperature (30 C.) for varied bath times. The lowest electrical resistivity value of the plated Cu lines was about 6 times greater than the bulk resistivity of Cu. This process presents an industrially viable way to fabricate Cu conductive fine patterns for flexible electronics at low temperature, and low cost.

A circuit forming method where a metal ink is ejected to a planned formation position of a first wiring at an upper face of a base material. Then, the metal ink is baked, and first wiring is formed. Further, a planned connection section of the first wiring and a second wiring is unbaked. The metal-ink is ejected over an upper face of the unbaked metal ink and a planned formation position of the second wiring at the upper face of the base material. Since the wettability of the upper face of the unbaked metal ink and the wettability of the upper face of the base material are equal to each other, the ejected metal ink ejected and the unbaked metal ink are not separated from each other, so that it is possible to properly connect the first wiring and the second wiring to each other.

An aliphatic polycarbonate resin for forming a partition containing a constituent unit represented by the formula (1):

##STR00001##

wherein R.sup.1, R.sup.2, R.sup.3, and R.sup.4 are each independently a hydrogen atom, an alkyl group having one or more carbon atoms, an alkoxyalkyl group having two or more carbon atoms, an aryl group, or an aryloxyalkyl group; at least one of R.sup.1, R.sup.2, R.sup.3, and R.sup.4 is an alkyl group having two or more carbon atoms, an alkoxyalkyl group having two or more carbon atoms, an aryl group, or an aryloxyalkyl group; and R.sup.1, R.sup.2, R.sup.3, and R.sup.4 may be the same or different; and the aliphatic polycarbonate resin has a contact angle against water of 75 or more. Also disclosed is a partition material including the aliphatic polycarbonate resin, a substrate, a method of producing the substrate, a method for producing a wiring substrate, and a wiring forming method.

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.