H05K2203/143

Hermetic metallized via with improved reliability

An article includes a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and at least one via extending through the substrate from the first major surface to the second major surface over an axial length in an axial dimension. The article also includes a metal connector disposed within the via that hermetically seals the via. The article has a helium hermeticity of less than or equal to 1.0×10.sup.−8 atm-cc/s after 1000 thermal shock cycles, each of the thermal shock cycle comprises cooling the article to a temperature of −40° C. and heating the article to a temperature of 125° C., and the article has a helium hermeticity of less than or equal to 1.0×10.sup.−8 atm-cc/s after 100 hours of HAST at a temperature of 130° C. and a relative humidity of 85%.

HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY

According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.

A PCB STRUCTURE FOR EMBEDDING ELECTRONIC COMPONENTS

A PCB, printed circuit board, structure for forming at least one embedded electronic component. The structure comprises a multi-layer PCB board comprising at least one through-hole via, the via comprising a plurality of electrodes vertically aligned within the via, each electrode comprising a plated ring; and an isolation section separating each of the electrodes.

Implementing backdrilling elimination utilizing anti-electroplate coating

A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill vias during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a plug is inserted into each via and the plug is lowered to a depth just below a desired signal trace layer. A thin anti-electroplate coating is applied onto the walls of the via below the signal trace. Then the plugs are removed and a standard board plating process for the PCB is performed.

HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY

According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 m at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 m at the second major surface and fully fills the via between the first cavity and the second cavity.

AQUEOUS ALKALINE CLEANER SOLUTION FOR GLASS FILLER REMOVAL AND METHOD

The invention relates to an aqueous alkaline cleaner solution for glass filler removal comprising: (a) at least one non-ionic surfactant selected from the group consisting of saturated branched or unbranched C5 to C12 carboxylic acid or salt thereof, wherein the concentration of the (a) at least one surfactant is from 0.9 to 1.7 g/L; (b) at least one surfactant selected from the group consisting of saturated branched or unbranched C5 to C12 alkyl having a negatively charged group selected from sulfate, sulfite, sulfonate, phosphate, phosphite and carbonate, and saturated C3-C8 alkyl amino carboxylate; (c) at least one compound having at least one hydroxyl group and at least one COC group selected from the group consisting of alkoxylated C5-C12 alkanol and glycosidic C5-C12 alkanol; and (d) alkali metal hydroxide, wherein the concentration of the (d) alkali metal hydroxide is from 65 to 200 g/L; and a method for use.

3D INTERPOSER WITH THROUGH GLASS VIAS - METHOD OF INCREASING ADHESION BETWEEN COPPER AND GLASS SURFACES AND ARTICLES THEREFROM

In some embodiments, a method comprises leaching a surface of a glass or glass ceramic substrate to form a leached layer. The glass or glass ceramic substrate comprises a multi-component material. The material has a bulk composition, in mol % on an oxide basis: 51% to 90% SiO.sub.2; 10% to 49% total of minority components RO.sub.x. Leaching comprises selectively removing components RO.sub.x of the glass or glass ceramic substrate preferentially to removal of SiO.sub.2. In the leached layer, the RO.sub.x concentration is 50% or less than the RO.sub.x concentration of the bulk composition.

HERMETIC METALLIZED VIA WITH IMPROVED RELIABILITY

An article includes a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and at least one via extending through the substrate from the first major surface to the second major surface over an axial length in an axial dimension. The article also includes a metal connector disposed within the via that hermetically seals the via. The article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 1000 thermal shock cycles, each of the thermal shock cycle comprises cooling the article to a temperature of 40 C. and heating the article to a temperature of 125 C., and the article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 100 hours of HAST at a temperature of 130 C. and a relative humidity of 85%.

PACKAGING SUBSTRATE FOR SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND METHOD
20190172782 · 2019-06-06 · ·

A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.

SINGLE LAMINATION BLIND AND METHOD FOR FORMING THE SAME
20190141840 · 2019-05-09 ·

A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.