An elongated wired circuit board including a plurality of wires arranged in parallel, wherein the plurality of wires each includes a first linear portion extending in a first linear direction, a second linear portion extending in a second linear direction, and a connection portion, the connection portion includes a first side, a second side, a third side, and a fourth side, length y1 and length S satisfy 0<y1<S, length y1 extending from the first corner portion reaching the first widthwise other end edge of the first linear portion, and length S extending from the first widthwise other end edge of the first linear portion of one wire, and the predetermined angle θ satisfies 0<θ<1 deg.

A component carrier includes an electrically insulating layer structure having a first main surface and a second main surface with a through hole extending through the electrically insulating layer structure between the first main surface and the second main surface. An electrically conductive bridge structure connects opposing sidewalls of the electrically insulating layer structure delimiting the through hole. A vertical thickness of the electrically insulating layer structure is not more than 200 μm and a narrowest vertical thickness of the bridge structure is at least 20 μm.

This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.

A wiring board manufacturing method includes: forming a first groove structure in a first principal surface of a base by scanning with laser light in a first irradiation pattern such that the first groove structure has a first width; irradiating an inside of the first groove structure with laser light in a second irradiation pattern that is different from the first irradiation pattern to form recessed portions inside the first groove structure; and forming a first wiring pattern by filling the first groove structure with a first electrically-conductive material to form a first wiring pattern whose shape matches with a shape of the first groove structure in a top view.

A method of manufacturing component carriers is disclosed. The method includes providing a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, forming a first hole in a core of the stack and subsequently embedding a first component in the first hole, thereafter forming a second hole in the same core of the stack and subsequently embedding a second component in the second hole. A component carrier has a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A first hole is formed in a core of the stack. A first component is embedded in the first hole. A second hole is formed in the same core of the stack and subsequently a second component is embedded in the second hole.

A printed wiring board includes an insulating layer, a conductor layer formed on the insulating layer and including first and second pads, a solder resist layer formed on the insulating layer, covering the conductor layer and exposing the first and second pads to form the second pad having diameter smaller than diameter of the first pad, a first bump formed on the first pad and including first base and top plating layers such that the first base layer has embedded portion in the resist layer and exposed portion and having diameter substantially equal to or smaller than diameter of the embedded portion, and a second bump formed on the second pad and including second base and top plating layers such that the second base layer has embedded portion in the resist layer and exposed portion and having diameter substantially equal to or smaller than diameter of the embedded portion.

A method is disclosed for applying an electrical conductor to a solar cell, which comprises providing a flexible membrane with a pattern of groove formed on a first surface thereof, and loading the grooves with a composition comprising conductive particles. The composition is, or may be made, electrically conductive. Once the membrane is loaded, the grooved first surface of the membrane is brought into contact with a front or/and back of a solar cell. A pressure is then applied between the solar cell and the membrane(s) so that the composition loaded to the grooves adheres to the solar cell. The membrane(s) and the solar cell are separated and the composition in the groove is left on the solar cell surface. The electrically conductive particles in the composition are then sintered or otherwise fused to form a pattern of electrical conductor on the solar cell, the pattern corresponding to the pattern formed in the membrane(s).

A circuit forming method where a metal ink is ejected to a planned formation position of a first wiring at an upper face of a base material. Then, the metal ink is baked, and first wiring is formed. Further, a planned connection section of the first wiring and a second wiring is unbaked. The metal-ink is ejected over an upper face of the unbaked metal ink and a planned formation position of the second wiring at the upper face of the base material. Since the wettability of the upper face of the unbaked metal ink and the wettability of the upper face of the base material are equal to each other, the ejected metal ink ejected and the unbaked metal ink are not separated from each other, so that it is possible to properly connect the first wiring and the second wiring to each other.

A component carrier includes an electrically insulating layer structure, a first electrically conductive layer structure, a second electrically conductive layer structure, and a laser through-hole with an electrically conductive medium filling at least part of the through-hole. The first electrically conductive layer structure covers a first side of the electrically insulating layer structure and has a first window extending through the first electrically conductive layer structure formed by etching using a conformal mask. The second electrically conductive layer structure covers an opposed side of the electrically insulating layer structure and has a second window extending through the second electrically conductive layer structure formed by etching using a conformal mask. The laser through-hole extends through the electrically insulating layer structure. At least a portion of at least one sidewall of the electrically conductive layer structures delimiting the windows is tapered.

Systems and methods for applying solder to a pin. The methods comprising: disposing a given amount of solder on a non-wetable surface of a planar substrate; aligning the pin with the solder disposed on the non-wetable surface of the planar substrate; inserting the pin in the solder; and performing a reflow process to cause the solder to transfer from the planar substrate to the pin.