Patent classifications
H10K10/82
Monomolecular transistor
A monomolecular transistor including a first electrode including a first electrode layer and a first metal particle arranged at one end of the first electrode layer, a second electrode including a first electrode layer and a first metal particle arranged at one end of the first electrode layer, a third electrode insulated from the first electrode and the second electrode, a π-conjugated molecule having a π-conjugated skeleton. The first metal particle and the second metal particle face each other. The third electrode is arranged adjacent to the gap in which the first metal particle and the second metal particle face each other, and is spaced from the first metal particle and the second metal particle, the π-conjugated molecule is arranged in a gap between the first metal particle and the second metal particle.
ORGANIC ELECTROCHEMICAL TRANSISTOR HAVING AN IMPROVED CONDUCTIVE CHANNEL
An organic electrochemical device including a substrate on which a source and drain are located, a gate electrode, and either a conductive channel of at least one organic conductive track or a conductive channel including at least one organic conductive track. Also, a method of manufacturing the organic electrochemical device.
Carbon Nanotube Based Radio Frequency Devices
High-performance carbon nanotube (CNT) based millimeter-wave transistor technologies and demonstrate monolithic millimeter-wave integrated circuits (MMICs) based thereon, and methods and processes for the fabrication thereof are also provided. CNT technologies and MMICs demonstrate improved power efficiency, linearity, noise and dynamic range performance over existing GaAs, SiGe and RF-CMOS technologies. Methods and processes in CNT alignment and deposition, material contact and doping are configured to fabricate high quality CNT arrays beyond the current state-of-the-art and produce high performance RF transistors that are scalable to wafer size to enable fabrication of monolithic integrated circuits based on CNTs.
FAN-OUT WIRING STRUCTURE OF DISPLAY PANEL AND DISPLAY PANEL
A fan-out wiring structure of a display panel is configured to electrically connect a signal transmission interface of a driving circuit to a signal receiving interface of a display area of the display panel. The fan-out wiring structure includes a first wiring layer and a second wiring layer. The first and the second wiring layers both define an extending area, a connecting area, and a bent area disposed between the extending area and the connecting area. The extending area and the connecting area of the first wiring layer each have a plurality of metal wires, and the bent area of the first wiring layer has a plurality of flexible wires. Each of the flexible wires is made of an organic electrically conductive material, and opposite ends of each of the flexible wires are connected to corresponding metal wires in the extending area and the connecting area, respectively.
Water-soluble diacetylene, photolithography composition comprising water-soluble diacetylene monomer and conductive polymer, and fine pattern preparation method using same
Provided are a novel water-soluble diacetylene monomer, a composition for photolithography including the novel water-soluble diacetylene monomer and a conductive polymer, and a method of forming micropatterns using the composition. The water-soluble diacetylene monomer may not aggregate even when mixed with a water-soluble conductive polymer. Accordingly, a uniform composition for photolithography can be prepared by mixing a water-soluble conductive polymer with the diacetylene monomer, and micropatterns can be formed using the composition. More particularly, when the composition is formed into a thin film and then is irradiated with light, only light-irradiated portions of the diacetylene monomer are selectively crosslinked due to photopolymerization, thereby resulting in insoluble negative-type micropatterns.
Organic light emitting diode display
An organic light emitting diode display is provided that may include a first substrate, a plurality of electrodes on the first substrate and spaced apart from each other, a pixel defining layer on the plurality of electrodes, spacers on the pixel defining layer, and a second substrate on the spacers. The pixel defining layer includes a plurality of openings spaced apart from each other and respectively open to the plurality of electrodes. The spacers on the pixel defining layer are at crossing points of a plurality of virtual lines, the spacers crossing spaces between adjacent openings of the plurality of openings.
Method for manufacturing field effect transistor and method for manufacturing wireless communication device
Provided is a method for manufacturing a field-effect transistor, the method including the steps of: forming a gate electrode on the surface of a substrate; forming a gate insulating layer on the gate electrode; forming a conductive film containing a conductor and a photosensitive organic component by a coating method on the gate insulating layer; exposing the conductive film from the rear surface side of the substrate with the gate electrode as a mask; developing the exposed conductive film to form a source electrode and a drain electrode; and forming a semiconductor layer by a coating method between the source electrode and the drain electrode. This method makes it possible to provide an FET, a semiconductor device, and an RFID which can be prepared by a simple process, and which have a high mobility, and have a gate electrode and source/drain electrodes aligned with a high degree of accuracy.
Memory cell and forming method thereof
A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.
MOLECULAR ELECTRONIC DEVICE
A molecular electronic device (10) includes a framework of polynucleotides (3), one or more molecular electronic components (4) and one or more electrical contacts (7). The molecular electronic components and the electrical contacts are each connected to the plurality of polynucleotides such that the molecular electronic components and the electrical contacts are located with respect to the framework and with respect to each other. This forms a coupling between the electrical contacts and the molecular electronic components.