An embodiment spin-orbit torque device array includes a plurality of single devices, each device including a non-magnetic layer, a magnetic layer bonded to the non-magnetic layer, and an upper layer bonded to the magnetic layer, wherein the upper layer includes oxide, and wherein a magnetization state of each of the single devices has only two states, the two states being an up state and a down state.

An embodiment magnetic memory device based on perpendicular exchange bias includes a non-magnetic layer, a ferromagnetic layer bonded on the non-magnetic layer, wherein a magnetization direction of the ferromagnetic layer is randomly distributed, and an anti-ferromagnetic layer bonded on the ferromagnetic layer. An embodiment method of manufacturing a magnetic memory device includes preparing the magnetic memory device based on perpendicular exchange bias, the preparing including bonding a ferromagnetic layer on a non-magnetic layer and bonding an anti-ferromagnetic layer on the ferromagnetic layer, and demagnetizing the ferromagnetic layer of the magnetic memory device, wherein a magnetization direction of the ferromagnetic layer is randomly distributed.

An embodiment magnetic memory device based on perpendicular exchange bias includes a non-magnetic layer, a ferromagnetic layer bonded on the non-magnetic layer, wherein a magnetization direction of the ferromagnetic layer is randomly distributed, and an anti-ferromagnetic layer bonded on the ferromagnetic layer. An embodiment method of manufacturing a magnetic memory device includes preparing the magnetic memory device based on perpendicular exchange bias, the preparing including bonding a ferromagnetic layer on a non-magnetic layer and bonding an anti-ferromagnetic layer on the ferromagnetic layer, and demagnetizing the ferromagnetic layer of the magnetic memory device, wherein a magnetization direction of the ferromagnetic layer is randomly distributed.

A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F.sup.2 and 4F.sup.2.

A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F.sup.2 and 4F.sup.2.

There is provided a method 100 of producing an electronic device precursor 200, the method 100 comprising: (i) providing 105 a plasma-etchable layer structure 210 on a plasma-resistant substrate 205, wherein the layer structure 210 has an exposed upper surface; (ii) patterning 110 a plasma-resistant dielectric 215 onto the exposed upper surface to form an intermediate having at least one covered region and at least one uncovered region of the layer structure 210; (iii) subjecting the intermediate to plasma etching 115, whereby the at least one uncovered region of the layer structure 210 is etched away to form at least one covered region of the layer structure 210 having an exposed edge surface; (iv) forming 120 an ohmic contact 220a, 220b in direct contact with a portion of the exposed edge surface; wherein the plasma-etchable layer structure 210 comprises one or more graphene layers which extend across the covered regions of the layer structure 210 to the exposed edge surface.

There is provided a method 100 of producing an electronic device precursor 200, the method 100 comprising: (i) providing 105 a plasma-etchable layer structure 210 on a plasma-resistant substrate 205, wherein the layer structure 210 has an exposed upper surface; (ii) patterning 110 a plasma-resistant dielectric 215 onto the exposed upper surface to form an intermediate having at least one covered region and at least one uncovered region of the layer structure 210; (iii) subjecting the intermediate to plasma etching 115, whereby the at least one uncovered region of the layer structure 210 is etched away to form at least one covered region of the layer structure 210 having an exposed edge surface; (iv) forming 120 an ohmic contact 220a, 220b in direct contact with a portion of the exposed edge surface; wherein the plasma-etchable layer structure 210 comprises one or more graphene layers which extend across the covered regions of the layer structure 210 to the exposed edge surface.

A graphene Hall sensor for operation at cryogenic temperatures is provided. The graphene Hall sensor comprises a substrate, a graphene sheet, a dielectric layer, a first pair of electrical contacts, and a second pair of electrical contacts. The graphene sheet is provided on the substrate. The dielectric layer is provided on the graphene sheet. The graphene sheet and the dielectric layer share a continuous outer edge surface. The first pair of electrical contacts are in electrical contact with the graphene sheet and spaced apart along a first direction. The second pair of electrical contacts are in electrical contact with the graphene sheet and spaced apart along a second direction. The first direction is perpendicular to the second direction, wherein a path along the first direction between the first pair of electrical contacts crosses a path along the second direction between the second pair of electrical contacts. The graphene sheet has a sheet carrier density in the range of 2?10.sup.11 cm.sup.?2 to 1?10.sup.13 cm.sup.?2.

A semiconductor device includes ferromagnetic, magnetostrictive layer that exhibits a biaxial magnetic anisotropy and an underlying structure exhibits a spin Hall effect to provide a conversion between electrical energy and magnetic energy with more than two distinctive magnetic states, wherein the underlying structure includes a piezoelectric material structure and a spin Hall metal layer.

A semiconductor device includes ferromagnetic, magnetostrictive layer that exhibits a biaxial magnetic anisotropy and an underlying structure exhibits a spin Hall effect to provide a conversion between electrical energy and magnetic energy with more than two distinctive magnetic states, wherein the underlying structure includes a piezoelectric material structure and a spin Hall metal layer.