According to various implementations of the invention, high quality a-axis XBCO may be grown with low surface roughness. According to various implementations of the invention, low surface roughness may be obtained by: 1) adequate substrate preparation; 2) calibration of flux rates for constituent atoms; and/or 3) appropriate control of temperature during crystal growth. According to various implementations of the invention, a wafer comprises a smoothing layer of c-axis XBCO; a first conducting layer of a-axis XBCO formed on the smoothing layer; an insulating layer formed on the first conducting layer; and a second conducting layer of a-axis XBCO formed on the insulating layer, where, for a same surface roughness, a thickness of the smoothing layer and the first conducting layer combined is greater than a thickness of the first conducting layer without the smoothing layer.

A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

In various embodiments, superconducting wires incorporate diffusion barriers composed of Ta alloys that resist internal diffusion and provide superior mechanical strength to the wires.

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

A method of an embodiment includes forming a capacitor pad for a nonlinear resonator. In an embodiment, the method includes comparing a resonance frequency of the nonlinear resonator to a target frequency to determine whether the resonance frequency falls within a range of the target frequency. A device of an embodiment includes a first capacitor pad comprising a superconducting material, the first capacitor pad configured to couple to a first end of a logic circuit element. In an embodiment, the device includes a second capacitor pad comprising a second superconducting material, the capacitor pad configured to couple to a second end of the logic circuit element. In an embodiment, the second capacitor pad includes a first portion; a second portion; and a bridge configured to electrically connect the first portion and the second portion.

A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); a predetermined signal line (w1) arranged in the wiring layer of the quantum chip (111); first shield wires (ws1) arranged in the wiring layer of the quantum chip (111) along the predetermined signal line (w1); a second shield wire (ws2) arranged in the wiring layer of the interposer (112); and a second connection part (150) that is provided between the interposer (112) and the quantum chip (111) so as to contact the first shield wires (ws1) and the second shield wire (ws2).

One embodiment includes a computer interconnect system. The system includes a first cable comprising a first superconducting signal line formed from a superconductor material to propagate at least one signal and a second cable comprising a second superconducting signal line formed from the superconductor material to propagate the respective at least one signal. The system also includes an interconnect structure configured to contact each of the first and second cable and comprising a third superconducting signal line formed from the superconductor material and configured to propagate the respective at least one signal between the respective first and second superconducting signal line. The system further includes at least one interconnect contact disposed on the first, second, and third at least one superconducting signal line at a contact portion between each of the at least one first and third superconducting signal lines and the at least second and third superconducting signal lines.

A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.

A system and method for fabricating accelerator cavities comprises forming at least two half cavities and joining the half cavities with a longitudinal seal. The half cavities can comprise at least one of aluminum, copper, tin, and copper alloys. The half cavities can be coated with a superconductor or combination of materials configured to form a superconductor coating.

A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.