A vertical Josephson junction device includes a substrate, and an epitaxial stack formed on the substrate. The vertical Josephson junction device includes a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack, the second superconducting electrode being separated from the first superconducting electrode by a dielectric layer. In operation, the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction.

Materials with etch selectivity with respect to one another and one or more additional etch-stop layers are used in a Josephson junction structure to allow for integration with a Josephson junction with supporting structures such as resistors. Selective etch processes compatible with high volume manufacturing are used to pattern various layers of the Josephson junction structure to provide a Josephson junction, which is electrically coupled to a support structure.

Compositions comprising a) one or more amorphous superconductor layers bound to one or more flexible substrate layers, or b) one or more superconductor layers bound to one or more layers of a high dielectric material are disclosed. Furthermore, provided herein are articles comprising one or more compositions of the invention and method of manufacturing thereof.

According to one embodiment, an electronic circuit includes a first nonlinear element, a second nonlinear element, and a third nonlinear element. The first nonlinear element includes a first element Josephson junction provided in a first region of a first surface including the first region and a second region. The second nonlinear element includes a second element Josephson junction provided in the second region. The third nonlinear element includes a Josephson junction circuit. At least a part of the Josephson junction circuit is provided on a second surface. The second surface is separated from the first surface in a first direction crossing the first surface. The second surface is along the first surface. The third nonlinear element is configured to be coupled with the first nonlinear element. The third nonlinear element is configured to be coupled with the second nonlinear element.

A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

The method that includes the step of a cleaning a surface of a silicon wafer and forming a sacrificial layer on top of the silicon wafer. The wafer undergoes further processing, wherein the processing includes forming at least one layer directly on top of the sacrificial layer. Immediately prior to the insertion into a dilute refrigeration unit removing a portion of the sacrificial layer by exposing the portion of the sacrificial layer to a solvent.

The method that includes cleaning the surface of a silicon wafer, forming a sacrificial layer on top of the silicon wafer; forming at least one window in the sacrificial layer exposing the surface of the silicon wafer, and processing the silicon wafer, wherein the processing includes forming at least one layer in the at least window, such that, wherein the at least one layer includes a first section that is direct contact with the silicon wafer and the walls of the at least one window created by the sacrificial layer, a main section that extends from the first section, and a bump out section that extends from the sides of the main section and the bottom surface of the bump out section is in contact with the sacrificial layer. Prior to the insertion into a dilute refrigeration unit removing the sacrificial layer by exposing it to a solvent, wherein the removal of the sacrificial layer causes the bottom surface of the bump section, the side portion of the first section, and the top surface of the silicon form a space without material.

A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (208), forming a first resist layer (210) on the dielectric substrate, forming a second resist layer (212) on the first resist layer, and forming a third resist layer (214) on the second resist layer. The first resist layer includes a first opening (216) extending through a thickness of the first resist layer, the second resist layer includes a second opening (218) aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening (220) aligned over the second opening and extending through a thickness of the third resist layer.

Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb.sub.2O.sub.5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.