A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.

A ceramic electronic device includes an element body and an external electrode. The element body is formed by laminating a ceramic layer and an internal electrode layer. The external electrode is electrically connected to at least one end of the internal electrode layer. The external electrode includes a baked electrode layer. The baked electrode layer includes a first region and a second region. The first region is contacted with an end surface of the element body and located near a joint boundary with the element body. The second region is located outside the first region and constituting an outer surface of the baked electrode layer. The first region includes a first glass having a predetermined composition. The second region includes a second glass having a predetermined composition.

A multilayer ceramic capacitor includes a laminate and

an external electrode connected to the internal electrode layer. The laminate includes a central layer portion in which an internal electrode layer and a dielectric ceramic layer are alternately laminated, and a covering portion covering an outer surface of the central layer portion in the lamination direction and the width direction. A region where the main surface meets the lateral surface in the laminate is defined as a corner portion that is rounded, and a distance from the corner portion to an internal electrode closest to the corner portion is about 20 .Math.m or less.

A multilayer ceramic capacitor includes a laminate and

an external electrode connected to the internal electrode layer. The laminate includes a central layer portion in which an internal electrode layer and a dielectric ceramic layer are alternately laminated, and a covering portion covering an outer surface of the central layer portion in the lamination direction and the width direction. A region where the main surface meets the lateral surface in the laminate is defined as a corner portion that is rounded, and a distance from the corner portion to an internal electrode closest to the corner portion is about 20 .Math.m or less.

A low inductance component may include a multilayer, monolithic device including a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination. The lead(s) may be coupled with the first active termination, second active termination, and/or the at least one ground termination. The lead(s) may have respective length(s) and maximum width(s). A ratio of the length(s) to the respective maximum width(s) of the lead(s) may be less than about 20.

A multilayer ceramic capacitor (MLCC) includes a body including first dielectric layers and second dielectric layers, the body including first to sixth surfaces, a second surface, a third surface, a fourth surface, a fifth surface and a sixth surface; first internal electrodes disposed on the first dielectric layers, exposed to the third surface, the fifth surface, and the sixth surface, and spaced apart from the fourth surface by first spaces; second internal electrodes disposed on the second dielectric layers to oppose the first internal electrodes with the first dielectric layers or the second dielectric layers interposed therebetween, exposed to the fourth surface, the fifth surface, and the sixth surface, and spaced apart from the third surface by second spaces; first dielectric patterns disposed in at least a portion of the first spaces, and second dielectric patterns disposed in at least a portion of the second spaces; and lateral insulating layers.

A multilayer ceramic capacitor (MLCC) includes a body including first dielectric layers and second dielectric layers, the body including first to sixth surfaces, a second surface, a third surface, a fourth surface, a fifth surface and a sixth surface; first internal electrodes disposed on the first dielectric layers, exposed to the third surface, the fifth surface, and the sixth surface, and spaced apart from the fourth surface by first spaces; second internal electrodes disposed on the second dielectric layers to oppose the first internal electrodes with the first dielectric layers or the second dielectric layers interposed therebetween, exposed to the fourth surface, the fifth surface, and the sixth surface, and spaced apart from the third surface by second spaces; first dielectric patterns disposed in at least a portion of the first spaces, and second dielectric patterns disposed in at least a portion of the second spaces; and lateral insulating layers.

A multilayer ceramic electronic component includes a ceramic body including first and second internal electrodes disposed to face each other and a dielectric layer interposed therebetween. When an average thickness of the dielectric layer is denoted as ‘td,’ an average thickness of the first and second internal electrodes is denoted as ‘te,’ and a standard deviation of thicknesses of an internal electrode, measured at a plurality of points in a predetermined region of the internal electrode, is denoted as ‘σte,’ a ratio of the standard deviation of thicknesses of the internal electrode to the average thickness of the dielectric layer, which is denoted as ‘σte/td,’ satisfies 0.12≤σte/td≤0.21.

A multilayer ceramic electronic component includes a ceramic body including first and second internal electrodes disposed to face each other and a dielectric layer interposed therebetween. When an average thickness of the dielectric layer is denoted as ‘td,’ an average thickness of the first and second internal electrodes is denoted as ‘te,’ and a standard deviation of thicknesses of an internal electrode, measured at a plurality of points in a predetermined region of the internal electrode, is denoted as ‘σte,’ a ratio of the standard deviation of thicknesses of the internal electrode to the average thickness of the dielectric layer, which is denoted as ‘σte/td,’ satisfies 0.12≤σte/td≤0.21.

A multilayer electronic component includes a body including a dielectric layer and a first internal electrode and a second internal electrode and having first to sixth surfaces, a first external electrode including a first connection portion on the third surface, a first band portion on the first surface, and a third band portion on the second surface, a second external electrode including a second connection portion on the fourth surface, a second band portion on the first surface, and a fourth band portion on the second surface, an insulating layer disposed on the second surface and extending onto the first and second connection portions, a first plating layer disposed on the first band portion, and a second plating layer disposed on the second band portion. The insulating layer includes glass, and a region disposed on the second surface in the insulating layer has a convex shape in the first direction.