Patent classifications
H01G4/232
Multi-layer ceramic electronic component
A multi-layer ceramic electronic component includes: a ceramic body including first and second main surfaces facing in a first axis direction, first and second end surfaces facing in a second axis direction, and first and second internal electrodes; a first external electrode including a first cover portion covering the first end surface, and a first extended portion extending from the first cover portion to the second main surface; and a second external electrode including a second cover portion covering the second end surface, and a second extended portion extending from the second cover portion to the second main surface, the multi-layer ceramic electronic component satisfying that, when T.sub.1 represents a dimension of the ceramic body in the first axis direction and T.sub.2 represents a dimension of each extended portion in the first axis direction, T.sub.1+T.sub.2 is 50 μm or less, and T.sub.2/(T.sub.1+T.sub.2) is 0.32 or less.
COMPONENT BUILT-IN SUBSTRATE
A component built-in substrate includes a multilayer body and a substrate including a multilayer ceramic electronic component embedded therein. The multilayer ceramic electronic component includes a first connection portion that protrudes from the first external electrode, and a second connection portion that protrudes from the second external electrode. The substrate includes a core material. The multilayer ceramic electronic component including the first connection portion and the second connection portion includes a surface covered by the core material and embedded in the substrate. The first connection portion protrudes toward a surface of the substrate, and is not exposed at the surface of the substrate. The second connection portion protrudes toward the surface of the substrate, and is not exposed at the surface of the substrate.
COMPONENT BUILT-IN SUBSTRATE
A component built-in substrate includes a multilayer body and a substrate including a multilayer ceramic electronic component embedded therein. The multilayer ceramic electronic component includes a first connection portion that protrudes from the first external electrode, and a second connection portion that protrudes from the second external electrode. The substrate includes a core material. The multilayer ceramic electronic component including the first connection portion and the second connection portion includes a surface covered by the core material and embedded in the substrate. The first connection portion protrudes toward a surface of the substrate, and is not exposed at the surface of the substrate. The second connection portion protrudes toward the surface of the substrate, and is not exposed at the surface of the substrate.
Multilayer ceramic electronic component and method for manufacturing the same
In a multilayer ceramic electronic component, a stacked body includes a first outer layer and a first outermost internal electrode layer. The first outer layer defines a first main surface. The first outermost internal electrode layer is adjacent to the first outer layer. The first outermost internal electrode layer is in contact with a first external electrode at a first end surface. The thickness of the first outer layer at the first end surface is greater than the thickness of the first outer layer at the center or approximate center in a length direction.
Multilayer ceramic capacitor and mount structure for multilayer ceramic capacitor
A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers, first and second external electrodes provided on respective opposing end surfaces, and third and fourth external electrodes provided on any side surface. The internal electrode layers include first and second internal electrode layers connected to the first and second external electrodes, respectively, and third and fourth internal electrode layers connected to the third and fourth external electrodes, respectively. The third internal electrode layer is provided at a distance from the first internal electrode layer, and the fourth internal electrode layer is provided at a distance from the second internal electrode layer.
MULTILAYER CERAMIC ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME
A multilayer ceramic electronic device includes a multilayer chip having a plurality of internal electrode layers that face each other and a plurality of dielectric layers, each of which is sandwiched by two of the plurality of internal electrode layers, one end of at least one of the plurality of internal electrode layers being exposed at a side face of the multilayer chip, a first external electrode that is provided on the side face of the multilayer chip, is in contact with at least one of the each end of the plurality of internal electrode layers, and includes ceramic grains, and a second external electrode that is provided on the first external electrode, has a glass, and has a main component that is a same metal as that of the first external electrode.
MULTILAYER ELECTRONIC COMPONENT
A multilayer electronic component includes: a body including a dielectric layer and internal electrodes alternately disposed while having the dielectric layer interposed therebetween; a first external electrode including a first connection portion and first and third band portions extending from ends of the first connection portion; a second external electrode including a second connection portion and second and fourth band portions extending from the second connection portion; an insulating layer disposed on the first and second connection portions and covering a top surface of the body and the third and fourth band portions; first and second plating layers disposed on the first and second band portions, respectively. An end of the plating layer and an end of the insulating layer contact with each other, and a thickness of the end of the plating layer and a thickness of the end of the insulating layer decreases toward the contact point.
PCB WITH INTERNAL CAPACITORS AND A MULTILAYER CAPACITANCE PLANE
A capacitor device to store electrical charge is disclosed that includes a first unit of a first conductor layer fabricated from a first material. The first conductor layer is sandwiched between two dielectric layers. This assembly is layered on a second unit of a second conductor layer fabricated from a second material and sandwiched between two additional dielectric layers. The first conductor layers are all electrically connected to one another, and the second conductor layers being electrically connected to one another but are not electrically connected to the first conductor. Any multiple of first and second units may be utilized.
PCB WITH INTERNAL CAPACITORS AND A MULTILAYER CAPACITANCE PLANE
A capacitor device to store electrical charge is disclosed that includes a first unit of a first conductor layer fabricated from a first material. The first conductor layer is sandwiched between two dielectric layers. This assembly is layered on a second unit of a second conductor layer fabricated from a second material and sandwiched between two additional dielectric layers. The first conductor layers are all electrically connected to one another, and the second conductor layers being electrically connected to one another but are not electrically connected to the first conductor. Any multiple of first and second units may be utilized.
Multilayer ceramic electronic component including external electrode with multilayer structure
A multilayer ceramic capacitor includes an external electrode including an underlying electrode layer, a lower plating layer on the underlying electrode layer at a first end surface and a second end surface, and an upper plating layer on the lower plating layer. The underlying electrode layer is a thin film electrode including at least one selected from Ni, Cr, Cu, and Ti. The lower plating layer is a Cu plating layer including a lower layer region located closer to the multilayer body and an upper layer region located between the lower layer region and the upper plating layer, and the Cu plating layer in the lower layer region has a metal grain diameter smaller than that of the Cu plating layer located in the upper layer region.