A capacitive element is provided that includes a substrate, a lower electrode on the substrate, first upper electrodes disposed to face the lower electrode, second upper electrodes disposed to face the lower electrode, a dielectric layer disposed between the lower electrode and the first upper electrodes and between the lower electrode and the second upper electrodes, a first wiring conductor that connects the first upper electrodes, and a second wiring conductor that connects the second upper electrodes. The first and second upper electrodes are adjacent to each other in a surface direction along the lower electrode and in an X-axis direction, and the first and second upper electrodes are adjacent to each other in the surface direction along the lower electrode and in a Y-axis direction.

A capacitive element is provided that includes a substrate, a lower electrode on the substrate, first upper electrodes disposed to face the lower electrode, second upper electrodes disposed to face the lower electrode, a dielectric layer disposed between the lower electrode and the first upper electrodes and between the lower electrode and the second upper electrodes, a first wiring conductor that connects the first upper electrodes, and a second wiring conductor that connects the second upper electrodes. The first and second upper electrodes are adjacent to each other in a surface direction along the lower electrode and in an X-axis direction, and the first and second upper electrodes are adjacent to each other in the surface direction along the lower electrode and in a Y-axis direction.

A semiconductor device that includes a semiconductor substrate; a first capacitance section on the semiconductor substrate, the first capacitance section including a first electrode layer, a first dielectric layer, and a second electrode layer; a second capacitance section on the semiconductor substrate, the second capacitance section including a third electrode layer, a second dielectric layer, and a fourth electrode layer; a first external electrode; a second external electrode; a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L.sub.1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L.sub.2, wherein an electrostatic capacity C.sub.1 of the first capacitance section and an electrostatic capacity C.sub.2 of the second capacitance section are different, and L.sub.1/L.sub.2=0.8 to 1.2.

A power electronics system has a housing, a cooling device, a power semiconductor module and a capacitor device, wherein a cooling section of a capacitor connection device is in theinially conducting contact with a cooling surface of the cooling device.

A feedthrough for an AIMD includes a ferrule with an insulator hermetically sealing a ferrule opening, both cooperatively separating a body fluid side from a device side. A circuit board disposed adjacent to the insulator device side has a ground plate or ground trace electrically connected to a circuit board ground conductive pathway disposed in a circuit board ground via hole. An anisotropic conductive layer disposed between the circuit board and the insulator device side has an electrically insulative matrix supporting a plurality of electrically conductive particles. The anisotropic conductive layer has a first thickness where at least one first electrically conductive particle is longitudinally aligned and in electrical contact with the ferrule and the circuit board ground conductive pathway electrically connected to the at least one circuit board ground plate or ground trace. The anisotropic conductive layer has a second, greater thickness where the ferrule and the circuit board ground conductive pathway are not longitudinally aligned, and no electrically conductive particles are in electrical contact with the ferrule and the circuit board ground conductive pathway.

A feedthrough for an AIMD includes a ferrule with an insulator hermetically sealing a ferrule opening, both cooperatively separating a body fluid side from a device side. A circuit board disposed adjacent to the insulator device side has a ground plate or ground trace electrically connected to a circuit board ground conductive pathway disposed in a circuit board ground via hole. An anisotropic conductive layer disposed between the circuit board and the insulator device side has an electrically insulative matrix supporting a plurality of electrically conductive particles. The anisotropic conductive layer has a first thickness where at least one first electrically conductive particle is longitudinally aligned and in electrical contact with the ferrule and the circuit board ground conductive pathway electrically connected to the at least one circuit board ground plate or ground trace. The anisotropic conductive layer has a second, greater thickness where the ferrule and the circuit board ground conductive pathway are not longitudinally aligned, and no electrically conductive particles are in electrical contact with the ferrule and the circuit board ground conductive pathway.

A capacitor component includes a plurality of unit laminates, each comprising a body with a stacked structure including a plurality of internal electrodes and connection electrodes that extend in a stacking direction of the body and electrically connect to the plurality of internal electrodes, and pad portions between adjacent unit laminates to electrically connect the respective connection electrodes of the unit laminates above and below the pad portions to each other.

A capacitor component includes a plurality of unit laminates, each comprising a body with a stacked structure including a plurality of internal electrodes and connection electrodes that extend in a stacking direction of the body and electrically connect to the plurality of internal electrodes, and pad portions between adjacent unit laminates to electrically connect the respective connection electrodes of the unit laminates above and below the pad portions to each other.

A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.

A multilayer ceramic electronic component includes a ceramic body including a dielectric layer, and a first internal electrode and a second internal electrode facing each other with the dielectric layer interposed therebetween, and a first external electrode electrically connected to the first internal electrode, and a second external electrode electrically connected to the second internal electrode, disposed in an outer portion of the ceramic body, the first and second external electrodes comprise a first electrode layer including a conductive metal, a first plating layer disposed on the first electrode layer and including nickel (Ni), and a second plating layer disposed on the first plating layer and including tin (Sn), and a ratio (t1/t2) is within a range from 1.0 to 9.0, where t1 is a thickness of the first plating layer including nickel (Ni), and t2 is a thickness of the second plating layer including tin (Sn).