An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

There is provided an oxide semiconductor film composed of nanocrystalline oxide or amorphous oxide, wherein the oxide semiconductor film includes indium, tungsten and zinc, a content rate of tungsten to a total of indium, tungsten and zinc in the oxide semiconductor film is higher than 0.5 atomic % and equal to or lower than 5 atomic %, and an electric resistivity is equal to or higher than 10.sup.1 cm. There is also provided a semiconductor device including the oxide semiconductor film.

In a semiconductor device including an oxide semiconductor, the amount of oxygen vacancies is reduced. Moreover, electrical characteristics of a semiconductor device including an oxide semiconductor are improved. The semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, an oxide semiconductor film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the oxide semiconductor film; and over the transistor, a first insulating film covering the gate insulating film, the oxide semiconductor film, and the pair of electrodes; and a second insulating film covering the first insulating film. An etching rate of the first insulating film is lower than or equal to 10 nm/min and lower than an etching rate of the second insulating film when etching is performed at 25 C. with 0.5 weight % of hydrofluoric acid.

A manufacturing method of a semiconductor device including a step of forming a silicon layer over a formation substrate, a step of forming a resin layer over the silicon layer, a step of forming a transistor over the resin layer, a step of forming a conductive layer over the silicon layer and the resin layer, and a step of separating the formation substrate and the transistor. The resin layer has an opening over the silicon layer. The conductive layer is in contact with the silicon layer through the opening in the resin layer. In the step of separating the formation substrate and the transistor, the silicon layer is irradiated with light, so that silicon contained in the silicon layer reacts with a metal contained in the conductive layer, and a metal silicide layer is formed.

In a transistor including an oxide semiconductor film, movement of hydrogen and nitrogen to the oxide semiconductor film is suppressed. Further, in a semiconductor device using a transistor including an oxide semiconductor film, a change in electrical characteristics is suppressed and reliability is improved. A transistor including an oxide semiconductor film and a nitride insulating film provided over the transistor are included, and an amount of hydrogen molecules released from the nitride insulating film by thermal desorption spectroscopy is less than 510.sup.21 molecules/cm.sup.3, preferably less than or equal to 310.sup.21 molecules/cm.sup.3, more preferably less than or equal to 110.sup.21 molecules/cm.sup.3, and an amount of ammonia molecules released from the nitride insulating film by thermal desorption spectroscopy is less than 110.sup.22 molecules/cm.sup.3, preferably less than or equal to 510.sup.21 molecules/cm.sup.3, more preferably less than or equal to 110.sup.21 molecules/cm.sup.3.

A method for non-contact measurement of stress in a thin-film deposited on a substrate is disclosed. The method may include measuring first topography data of a substrate having a thin-film deposited thereupon. The method may also include comparing the first topography data with second topography data of the substrate that is measured prior to thin-film deposition. The method may further include obtaining a vertical displacement of the substrate based on the comparison between the first topography data and the second topography data. The method may also include detecting a stress value in the thin-film deposited on the substrate based on a fourth-order polynomial equation and the vertical displacement.

A method for non-contact measurement of stress in a thin-film deposited on a substrate is disclosed. The method may include measuring first topography data of a substrate having a thin-film deposited thereupon. The method may also include comparing the first topography data with second topography data of the substrate that is measured prior to thin-film deposition. The method may further include obtaining a vertical displacement of the substrate based on the comparison between the first topography data and the second topography data. The method may also include detecting a stress value in the thin-film deposited on the substrate based on a fourth-order polynomial equation and the vertical displacement.

A includes a switch TFT and a drive TFT. The switch TFT is formed of a first source and a first drain, a first gate, and a first etching stopper layer, and a first oxide semiconductor layer and first gate isolation layer sandwiched therebetween. The drive TFT is formed of a second source and a second drain, a second gate, and a second oxide semiconductor layer, and a first etching stopper layer and a second gate isolation layer sandwiched therebetween. The electrical properties of the switch TFT and the drive TFT are different. The switch TFT has a smaller subthreshold swing to achieve fast charge and discharge, and the drive TFT has a relatively larger subthreshold swing for controlling a current and a grey scale more precisely.

The present invention provides a method for manufacturing a TFT array substrate, comprises: providing a substrate; depositing a metal gate electrode, an insulating layer, and a metal oxide layer on a surface of the substrate; forming a first metal layer on a surface of the metal oxide layer; depositing a photoresist layer on the first metal layer and implementing a photolithography process to the first metal layer to be configured as a second metal layer, a channel is defined in the second metal layer; and a portion of the photomask vertically corresponding to the channel of the second metal layer is extended greater than the second metal layer.

The present disclosure provides an array substrate, its manufacturing method, and a display device. The method includes steps of forming a passivation layer on a base substrate, and forming a contact layer and a pixel electrode on the base substrate with the passivation layer through a single patterning process. The contact layer is made of an identical transparent conductive material to the pixel electrode.