TFT backplate structure comprising transistors having gate isolation layers of different thicknesses and manufacture method thereof

Abstract

A includes a switch TFT and a drive TFT. The switch TFT is formed of a first source and a first drain, a first gate, and a first etching stopper layer, and a first oxide semiconductor layer and first gate isolation layer sandwiched therebetween. The drive TFT is formed of a second source and a second drain, a second gate, and a second oxide semiconductor layer, and a first etching stopper layer and a second gate isolation layer sandwiched therebetween. The electrical properties of the switch TFT and the drive TFT are different. The switch TFT has a smaller subthreshold swing to achieve fast charge and discharge, and the drive TFT has a relatively larger subthreshold swing for controlling a current and a grey scale more precisely.

Claims

1. A thin-film transistor (TFT) backplate structure, comprising: a substrate; a first gate and a second gate on the substrate and spaced from each other in a sideway direction by a distance in between; a first gate isolation layer on the substrate and the first gate; a second gate isolation layer on the substrate and the second gate; a first oxide semiconductor layer provided on the first gate isolation layer and located exactly above the first gate; a first etching stopper layer on the first oxide semiconductor layer and the second gate isolation layer; a second oxide semiconductor layer provided on the second gate isolation layer and located exactly above the second gate; a first source and a first drain provided on the first gate isolation layer and the first etching stopper layer; a second source and a second drain provided on the first etching stopper layer and the second oxide semiconductor layer; a protective layer on the first source, the first drain, the second source, and the second drain; a pixel electrode on the protective layer; wherein the first source and the first drain are connected to the first oxide semiconductor layer and one of the first source and the first drain is connected to the second gate; the second source and the second drain are connected to the second oxide semiconductor layer; and the pixel electrode is connected to one of the second source and the second drain; and wherein the first source/the first drain, the first gate, and the first etching stopper layer, the first oxide semiconductor layer, and the first gate insulation layer that are between the first source/the first drain and the first gate collectively form a switching thin-film transistor and the second source/the second drain, second first gate, and the second oxide semiconductor layer, the first etching stopper layer, and the second gate insulation layer that are between the second source/the second drain and the second gate collectively form a driving thin-film transistor, the switching thin-film transistor and the driving thin-film transistor being arranged side by side and spaced from each other in the sideway direction, wherein in the side-by-side arranged switching thin-film transistor and driving thin-film transistor, the first etching stopper layer is located above the first oxide semiconductor layer and below the second oxide semiconductor layer such that the switching thin-film transistor and the driving thin-film transistor have different electrical properties.

2. The TFT backplate structure as claimed in claim 1, wherein the first etching stopper layer, the first oxide semiconductor layer, and the first gate isolation layer are sandwiched between the first source/the first drain and the first gate to form the switching thin-film transistor; and the second oxide semiconductor layer, the first etching stopper layer, and the second gate isolation layer are sandwiched the second source/the second drain and the second gate to form the driving thin-film transistor.

3. The TFT backplate structure as claimed in claim 2, wherein the driving thin-film transistor further comprises a second etching stopper layer provided on the second oxide semiconductor layer, and the second etching stopper layer, the second oxide semiconductor layer, the first etching stopper layer, and the second gate isolation layer are sandwiched between the second source/the second drain and the second gate to form the driving thin-film transistor.

4. The TFT backplate structure as claimed in claim 1, wherein the first and second oxide semiconductor layers comprises semiconductor layers made of the same material.

5. The TFT backplate structure as claimed in claim 4, wherein the first and second oxide semiconductor layers comprise indium gallium zinc oxide (IGZO) semiconductor layers.

6. The TFT backplate structure as claimed in claim 1, wherein the pixel electrode comprises an indium tin oxide (ITO) electrode.

Description

BRIEF DESCRIPTION OF THE DRAWING

(1) The technical solution, as well as beneficial advantages, of the present invention will be apparent from the following detailed description of an embodiment of the present invention, with reference to the attached drawings.

(2) In the drawings:

(3) FIG. 1 is a sectional diagram of a TFT backplate structure according to the first embodiment of the present invention;

(4) FIG. 2 is a sectional diagram of a TFT backplate structure according to the second embodiment of the present invention;

(5) FIG. 3 is a flowchart of a manufacture method of a TFT backplate structure according to the present invention;

(6) FIG. 4 is a diagram of Step 1 of the manufacture method of the TFT backplate structure according to the present invention;

(7) FIG. 5 is a diagram of Step 2 in the manufacture method of the TFT backplate structure according to the present invention;

(8) FIG. 6 is a diagram of Step 3 of the manufacture method of the TFT backplate structure according to the present invention;

(9) FIG. 7 is a diagram of Step 4 of the manufacture method of the TFT backplate structure according to the present invention;

(10) FIG. 8 is a diagram showing one embodiment of Step 5 of the manufacture method of the TFT backplate structure according to the present invention;

(11) FIG. 9 is a diagram showing another embodiment of Step 5 of the manufacture method of the TFT backplate structure according to the present invention;

(12) FIG. 10 is a diagram of Step 6 of the manufacture method of the TFT backplate structure according to the present invention;

(13) FIG. 11 is a diagram of Step 7 of the manufacture method of the TFT backplate structure according to the present invention; and

(14) FIG. 12 is a diagram of Step 8 of the manufacture method of the TFT backplate structure according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(15) In order to better understand the characteristics and technical aspect of the invention, reference is made to the following detailed description of the present invention in combination with the diagrams.

(16) Referring to FIG. 1, a first embodiment of a TFT backplate structure according to the present invention is shown. The TFT backplate structure comprises a substrate 1, a first gate 21 and a second gate 22 on the substrate 1 with a distance in between, a first gate isolation layer 31 on the substrate 1 and the first gate 21, a second gate isolation layer 32 on the substrate 1 and the second gate 22, a first oxide semiconductor layer 41 right over the first gate 21 and on the first gate isolation layer 31, a first etching stopper layer 51 on the first oxide semiconductor layer 41 and the second gate isolation layer 32, a second oxide semiconductor layer 42 right over the second gate 22 and on the second gate isolation layer 32, a first source/a first drain 61 on the first gate isolation layer 31 and the first etching stopper layer 51, a second source/a second drain 62 on the first etching stopper layer 51 and the second oxide semiconductor layer 42, a protective layer 7 on the first source/the first drain 61 and the second source/the second drain 62, a pixel electrode 8 on the protective layer 7.

(17) Both the first gate 21 and the second gate 22 are formed by patterning the same first metal film. The first gate isolation layer 31 and the second gate isolation layer 32 are formed by patterning the same gate isolation film. The first oxide semiconductor layer 41 is formed by patterning an oxide semiconductor film. The second oxide semiconductor layer 42 is formed by patterning another oxide semiconductor film. The first etching stopper layer 51 is formed by patterning an etching stopper film. Both the first source/the first drain 61 and the second source/the second drain 62 are formed by patterning the same second metal film.

(18) The first source/the first drain 61 are connected to the first oxide semiconductor layer 41 and the second gate 22; the second source/the second drain 62 are connected to the second oxide semiconductor layer 42; the pixel electrode 8 is connected to the second source/the second drain 62.

(19) The first source/the first drain 61, the first gate 21, and the first etching stopper layer 51, the first oxide semiconductor layer 41, the first gate isolation layer 31 sandwiched in between construct a switch TFT T1; the second source/the second drain 62, the second gate 22, and the second oxide semiconductor layer 42, the first etching stopper layer 51, the second gate isolation layer 32 sandwiched in between construct a drive TFT T2.

(20) The first gate isolation layer 31 is employed as an isolation layer of the first source/the first drain 61 and the first gate 21 of the switch TFT T1. The first etching stopper layer 51 and the second gate isolation layer 32 are employed as an isolation layer of the second source/the second drain 62 and the second gate 22. Structural differentiations exist between the switch TFT T1 and the drive TFT T2 thereby to make the electrical properties of the switch TFT T1 and the drive TFT T2 different: the switch TFT T1 possesses a smaller subthreshold swing S.S for fast charge and discharge; the drive TFT T2 possesses a relatively larger subthreshold swing S.S for controlling the current and the grey scale more precisely. Therefore, the TFT backplate structure can meet the demands of the practical usage to raise the performance of the TFT backplate in advance.

(21) Furthermore, both the first, the second oxide semiconductor layers 41, 42 are indium gallium zinc oxide (IGZO) semiconductor layers; and the pixel electrode 8 is an indium tin oxide (ITO) pixel electrode.

(22) Referring to FIG. 2, a second embodiment of the TFT backplate structure according to the present invention is shown. A difference of the second embodiment from the first embodiment is that the TFT backplate structure further comprises a second etching stopper layer 52 on the second oxide semiconductor layer 42. The second etching stopper layer 52 is formed by patterning another etching stopper film. Correspondingly, the drive TFT T2 is constructed by the second source/a second drain 62, the second gate 22, and the second etching stopper layer 52, the second oxide semiconductor layer 42, the first etching stopper layer 51, a second gate isolation layer 32 sandwiched in between. Other figures are the same as the first embodiment. The repeated description is omitted here.

(23) In comparison with the second embodiment, the first embodiment omits the second etching stopper layer 52 which can eliminate one mask process and raise the process efficiency.

(24) Referring to FIG. 3, the present invention further provides a manufacture method of a TFT backplate structure, comprising steps of:

(25) Step 1, as shown in FIG. 4, providing a substrate 1, and depositing a first metal film on the substrate 1, and patterning the first metal film to form a first gate 21 and a second gate 22 with a distance in between.

(26) Step 2, as shown in FIG. 5, depositing a gate isolation film on the substrate 1, the first gate 21 and the second gate 22 and patterning the gate isolation film to form a first gate isolation layer 31 and a second gate isolation layer 32.

(27) The first gate isolation layer 31 and the second gate isolation layer 32 formed in Step 2 have the same material and the same thickness.

(28) Step 3, as shown in FIG. 6, depositing an oxide semiconductor film on the substrate 1 of accomplishing Step 2 and patterning the oxide semiconductor film to form a first oxide semiconductor layer 41 right over the first gate 21 and on the first gate isolation layer 31.

(29) Specifically, the first oxide semiconductor layer 41 is an IGZO semiconductor layer.

(30) Step 4, as shown in FIG. 7, depositing an etching stopper film on the substrate 1 of accomplishing the step 3 and patterning the etching stopper film to form a first etching stopper layer 51 on the first oxide semiconductor layer 41 and the second gate isolation layer 32.

(31) Step 4 is different from the traditional process. The first etching stopper layer 51 is not only formed on the first oxide semiconductor layer 41 but also formed on the second gate isolation layer 32 to make the first etching stopper layer 51 completely cover the second gate isolation layer 32.

(32) Step 5, where FIG. 8 shows one embodiment of Step 5, depositing an oxide semiconductor film on the substrate 1 of accomplishing Step 4 and patterning the oxide semiconductor film to form a second oxide semiconductor layer 42 right over the second gate 22 and on the first etching stopper layer 51.

(33) Specifically, the second oxide semiconductor layer 42 is an IGZO semiconductor layer.

(34) FIG. 9 shows another embodiment of Step 5. Besides forming the second oxide semiconductor layer 42, the step further comprises depositing and patterning an etching stopper film on the second oxide semiconductor layer 42 to form a second etching stopper layer 52 on the second oxide semiconductor layer 42.

(35) In comparison with the embodiment shown in FIG. 9, the embodiment shown in FIG. 8 can eliminate and save one mask process and raise the process efficiency.

(36) Step 6, as shown in FIG. 10, depositing a second metal film on the substrate 1 of accomplishing Step 5 and patterning the second metal film to form a first source/a first drain 61, and a second source/a second drain 62.

(37) The first source/the first drain 61 are connected to the first oxide semiconductor layer 41 and the second gate 22, and the second source/the second drain 62 are connected to the second oxide semiconductor layer 42.

(38) After Step 6 is accomplished, the first source/the first drain 61, the first gate 21, and the first etching stopper layer 51, the first oxide semiconductor layer 41, the first gate isolation layer 31 sandwiched in between construct the switch TFT T1; the second source/the second drain 62, the second gate 22, and the second oxide semiconductor layer 42, the first etching stopper layer 51, the second gate isolation layer 32 sandwiched in between construct the drive TFT T2. Alternatively, the second source/the second drain 62, the second gate 22, and the second etching stopper layer 52, the second oxide semiconductor layer 42, the first etching stopper layer 51, the second gate isolation layer 32 sandwiched in between construct the drive TFT T2.

(39) Step 7, as shown in FIG. 11, forming a protective layer 7 on the first source/the first drain, and the second source/the second drain 61, 62.

(40) Step 8, as shown in FIG. 12, forming a pixel electrode 8 on the protective layer 7.

(41) The pixel electrode 8 is connected to the second source/the second drain 62.

(42) Specifically, the pixel electrode 8 is an ITO pixel electrode.

(43) Structural differences exist between the switch TFT T1 and the drive TFT T2 because the first etching stopper layer 51 is manufactured on the second gate isolation layer 32 according to the method: only the first gate isolation layer 31 exists between the first source/the first drain 61 and the first gate 21 of the switch TFT T1, and not only the second gate isolation layer 32 but also the first etching stopper layer 51 exist between the second source/the second drain 62 and the second gate 22. Accordingly, the switch TFT T1 and the drive TFT T2 have different electrical properties: the switch TFT possesses a smaller subthreshold swing S.S for fast charge and discharge; the drive TFT possesses a relatively larger subthreshold swing S.S for controlling the current and the grey scale more precisely.

(44) In conclusion, according to the TFT backplate structure of the present invention, by arranging the first gate isolation layer as an isolation layer between the source/the drain of the switch TFT and the gate, and arranging the first etching stopper layer and the second gate isolation layer as an isolation layer between the source/the drain of the drive TFT and the gate to make that the switch TFT and the drive TFT have different electrical properties. Accordingly, the switch TFT possesses a smaller subthreshold swing for fast charge and discharge, and the drive TFT possesses a larger subthreshold swing for controlling the current and the grey scale more precisely to raise the performance of the TFT backplate. According to the manufacture method of the TFT backplate structure, by forming the first etching stopper layer on the second gate isolation layer, the switch TFT and the drive TFT have different electrical properties to raise the performance of the TFT backplate.

(45) The above provide specific embodiments of the present invention, and the scope of the present invention is not limited to thereto. For persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.