A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

A method and an apparatus for bonding semiconductor substrates are provided. The apparatus includes a first support configured to carry a first semiconductor substrate and a second semiconductor substrate bonded to each other, a gauging component embedded in the first support and comprising a fiducial pattern, and a first sensor disposed proximate to the gauging component, and configured to emit a light source towards the fiducial pattern of the gauging component.

A wafer separating apparatus is provided which includes a wafer supporting member having an upper surface on which a bonded wafer formed of two wafers bonded with each other is placed; an arm portion arranged outside of the wafer supporting member, the arm portion being movable closer to and away from a bonded portion of the bonded portion of the bonded wafer supported by the supporting portion; and an inflating portion provided in an distal end portion of the arm portion, the inflating portion being inflatable in a direction intersecting the upper surface of the wafer supporting member.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

The present invention is a substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has at least a bond wafer including a silicon single crystal joined on a base wafer including a silicon single crystal, the base wafer includes CZ silicon having a resistivity of 0.1 Ωcm or lower and a crystal orientation of <100>, and the bond wafer has a crystal orientation of <111>. This provides a substrate for an electronic device, having a suppressed warp.

Methods for fabricating vertical cavity surface emitting lasers (VCSELs) on a large wafer are provided. An un-patterned epi layer form is bonded onto a first reflector form. The first reflector form includes a first reflector layer and a wafer of a first substrate type. The un-patterned epi layer form includes a plurality of un-patterned layers on a wafer of a second substrate type. The first and second substrate types have different thermal expansion coefficients. A resulting bonded blank is substantially non-varying in a plane that is normal to an intended emission direction of the VCSEL. A first regrowth is performed to form first regrowth layers, some of which are patterned to form a tunnel junction pattern. A second regrowth is performed to form second regrowth layers. A second reflector form is bonded onto the second regrowth layers, wherein the second reflector form includes a second reflector layer.

A method for fabricating semiconductor chip structures, which comprises steps of: providing plural slice units tiled with one another on a process carrier, wherein each slice unit is made from a wafer and includes a substrate with an outline, and a gap is formed between adjacent two of the slice units; planarizing tops of the slice units; accomplishing circuits on the slice units and turning them into circuited slice units; and forming plural semiconductor chip structures individually with each other by at least breaking down the circuited slice units; wherein a planar size of one slice unit is no less than that of a corresponding semiconductor chip structure, or the planar size of one slice unit is no less than multiple of the planar size of the corresponding semiconductor chip structure. A semiconductor carrier and a semiconductor chip structure made by the method are also provided.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields modulate the charge carriers and carrier density on a nanometer length scale, resulting in the formation of lateral p-n or p-i-n junctions, and variations thereof appropriate for device functions. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

A device, a system and a method for bonding two substrates. A first substrate holder has a recess and an elevation.

A method for producing a stacked structure comprises: a) providing a carrier substrate and an initial substrate, each having a front face and a back face, b) forming a buried weakened plane in the carrier substrate or in the initial substrate, by implanting light ions through the front face of either of the substrates, c) joining the carrier substrate and the initial substrate via their respective front faces, d) thinning the initial substrate via its back face to form a donor substrate e) providing a receiver substrate having a front face and a back face, f) joining the donor substrate and the receiver substrate via their respective front faces, and g) separating along the buried weakened plane, so as to form the stacked structure comprising the receiver substrate and a surface film including all or part of a donor layer originating from the initial substrate.