A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.

A quasi-vertical Schottky diode architecture includes a topside anode contact that connects to external circuitry through an airbridge finger, a thin mesa of semiconductor material with epilayers including a bottomside highly-doped layer, a bottomside ohmic contact directly below the anode, and a host substrate onto which the diode material is bonded by a thin adhesive layer. A method of fabricating the diode architecture includes preparation of the semiconductor wafer for processing (including initial etching to expose the highly-doped epilayer, deposition of metals and annealing to form the ohmic contact, application of the adhesive layer to the host substrate, thermal compression bonding of diode wafer and host wafer, with ohmic contact side facing host wafer to form a composite wafer, etching and formation of diode mesas to isolate devices on the host substrate, lithography and formation of topside anode contact and external circuitry on host wafer).

The present invention is a method for manufacturing a bonded SOI wafer, including: preparing, as a base wafer, a silicon single crystal wafer whose initial interstitial oxygen concentration is 15 ppma or more ('79ASTM); forming a silicon oxide film on a surface of the base wafer by heating the base wafer in an oxidizing atmosphere such that a feeding temperature at which the base wafer is fed into a heat treatment furnace for the heat treatment is 800° C. or more, and the base wafer is heated at the feeding temperature or higher; bonding the base wafer to the bond wafer with the silicon oxide film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a method for manufacturing a bonded SOI wafer by a base oxidation method which suppresses the formation of oxide precipitates in a base wafer while suppressing slip dislocation.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

A method for manufacturing an electrical device is disclosed. In an embodiment, the method includes providing a first layer of a first conductivity type, providing an intrinsic layer onto the first layer, providing one or more trenches into the intrinsic layer, filling the one or more trenches with a material of a second conductivity type opposite to the first conductivity type, and providing a second layer of a second conductivity type onto the intrinsic layer.

The present invention provides a method of manufacturing a bonded wafer, including performing RTA under an atmosphere containing hydrogen on a bonded wafer after separating the bond wafer constituting the bonded wafer, and subsequently performing a sacrificial oxidation process to reduce the thickness of the thin film, wherein the RTA is performed under conditions of a retention start temperature of more than 1150° C. and a retention end temperature of 1150° C. or less. The invention can inhibit the BMD density from increasing and sufficiently flatten the surface of a thin film when the thin film of the bonded wafer is flattened and thinned by the combination of the RTA and sacrificial oxidation processes.

A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.

A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.

In a high electron mobility transistor (HEMT), dielectric material may be included between edge portions of a HEMT gate and gate field plates in contact with a HEMT gate electrode. At least some portions of the HEMT gate and HEMT gate electrode remain in direct contact with one another, and the HEMT gate electrode and gate field plates may be further connected to a gate metal.

A method for bonding a first wafer onto a second wafer by molecular adhesion where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.