Disclosed are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises: a second source/drain layer (2), an insulation layer (3) and a first source/drain layer (1), which are sequentially arranged in a stacked manner; and a gate electrode (5) and a channel layer (4) surrounding the gate electrode (5), which are located in the first source/drain layer (1) and the insulation layer (3), wherein the channel layer (4) is in contact with the first source/drain layer (1) and the second source/drain layer (2); the first source/drain layer (1) comprises a first metal layer (11) and a second metal layer (12), the first metal layer (11) is close to the insulation layer (3), and the second metal layer (12) is away from the insulation layer (3); the material of the first metal layer (11) is a metal with a work function lower than that of molybdenum; and the material of the second metal layer (12) is a metal with a conductivity higher than 310.sup.6 S/m and an oxidation resistance not lower than that of molybdenum. By means of the thin-film transistor of a CAA architecture, the size of the transistor can be reduced, the power consumption of the transistor can be reduced, and the contact performance and the conductivity performance of the transistor can be improved.

Disclosed herein are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises a first source/drain layer (1); a second source/drain layer (3); an insulating layer (2), which is located between the first source/drain layer (1) and the second source/drain layer (3); a channel layer (4), which is embedded in the first source/drain layer (1) and the insulating layer (2); and a gate electrode (5), which is embedded in the channel layer (4), wherein an embedded end of the channel layer (4) is in contact with the second source/drain layer (3), and a top end of the channel layer (4) and a top end of the gate electrode (5) are both flush with the first source/drain layer (1). The thin-film transistor provided in the present disclosure is a CAA architecture in which an annular channel is arranged surrounding the gate electrode (5), such that the performance of the transistor can be improved, and the power consumption can be reduced; moreover, there is no gate electrode (5) in the horizontal direction covering the first source/drain layer (1), such that the parasitic capacitance and current leakage of the gate electrode can be reduced.

Provided are a thin film transistor, a display substrate and a display device, the thin film transistor includes: a gate on a base substrate; an active layer between the gate and the base substrate, the active layer includes a source contact portion, a drain contact portion and a middle portion therebetween, orthographic projections of the middle portion and the gate on the base substrate overlaps to form a first overlapping region, a material of the middle portion includes a metal oxide containing a doped element, a dissociation energy of the doped element from an oxygen element is greater than 500 Kj/mol; a source connected to the source contact portion and a drain connected to the drain contact portion, a ratio of an area of the orthographic projection of the gate on the base substrate to an area of the first overlapping region is less than or equal to 3.

A thin film transistor and a preparation method therefor, a memory, and a display. The thin film transistor comprises: a first source/drain layer (1), a first insulating layer (2), a second source/drain layer (3) and a second insulating layer (4) which are sequentially stacked; and a gate (6) and a channel layer (5) surrounding the gate (6), which are located in the second insulating layer (4), the second source/drain layer (3) and the first insulating layer (2). The channel layer (5) is in contact with the first source/drain layer (1), the first insulating layer (2), the second source/drain layer (3) and the second insulating layer (4). The thin film transistor is a CAA architecture of an annular channel surrounding the gate (6). Moreover, the leakage current of the gate (6) and the parasitic capacitance of the thin film transistor can be reduced by adding the second insulating layer (4) above the second source/drain layer (3).