An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.

Short-wave infrared (SWIR) focal plane arrays (FPAs) comprising a Si layer through which light detectable by the FPA reaches photodiodes of the FPA, at least one germanium (Ge) layer including a plurality of distinct photosensitive areas including at least one photosensitive area in each of a plurality of photosensitive photosites, each of the distinct photosensitive areas comprising a plurality of proximate steep structures of Ge having height of at least 0.5 μm and a height-to-width ratio of at least 2, and methods for forming same.

A stacked film is a stacked film including an oxide film, and a metal film provided on the oxide film, in which the oxide film includes a ZrO.sub.2 film of which a main surface is a (001) plane, the metal film includes a Pt film or a Pd film that has a single orientation and of which a main surface is a (001) plane, and a [100] axis of the ZrO.sub.2 film and a [100] axis of the metal film are parallel to an interface between the oxide film and the metal film, and the axes of both are parallel to each other.

An IC device includes a simultaneously formed capacitor and resistor structure. The capacitor and resistor may be located between a Back End of the Line (BEOL) interconnect stack and an external device interconnect pad of the IC device. The resistor may be used to step down a voltage applied across the resistor. The resistor may include one or more resistor plates that are formed simultaneously with a respective one or more plates of the capacitor. For example, a capacitor plate and a resistor plate may be patterned and formed from the same conductive sheet. Each of the resistor plates may be connected to one or more vertical interconnect accesses (VIA).

An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.

A semiconductor device includes a capacitor and a resistor. The capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process.

A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a first color conversion layer over each of a first plurality of light emitting diodes, a second color conversion layer over each of a second plurality of light emitting diodes, and a plurality of isolation walls separating adjacent micro-LEDs of the array. The micro-LEDs of the array are configured to generate illumination of the same wavelength range, the first color conversion layer converts the illumination to light of a first color, and the second color conversion layer converts the illumination to light of a different second color.