Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

A method is for detecting a condition associated with a final phase of a plasma dicing process. The method includes providing a non-metallic substrate having a plurality of dicing lanes defined thereon, plasma etching through the substrate along the dicing lanes, wherein during the plasma etching infrared emission emanating from at least a portion of the dicing lanes is monitored so that an increase in infrared emission from the dicing lanes is observed as the final phase of the plasma dicing operation is entered, and detecting the condition associated with the final phase of the plasma dicing from the monitored infrared emission.

A method is for detecting a condition associated with a final phase of a plasma dicing process. The method includes providing a non-metallic substrate having a plurality of dicing lanes defined thereon, plasma etching through the substrate along the dicing lanes, wherein during the plasma etching infrared emission emanating from at least a portion of the dicing lanes is monitored so that an increase in infrared emission from the dicing lanes is observed as the final phase of the plasma dicing operation is entered, and detecting the condition associated with the final phase of the plasma dicing from the monitored infrared emission.

A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

A coating for protecting a wafer from moisture and debris due to dicing, singulating, or handling the wafer is provided. A semiconductor sensor device comprises a wafer having a surface and at least one trench feature and the protective coating covering the trench feature. The trench feature comprises a plurality of walls and the walls are covered with the protective coating, wherein the walls of the trench feature are formed as a portion of the semiconductor sensor device. The semiconductor sensor device further comprises a patterned mask formed on the wafer before the trench feature is formed, wherein the protective coating is formed directly to the trench feature and the patterned mask. The semiconductor sensor device is selected from a group consisting of a MEMS die, a sensor die, a sensor circuit die, a circuit die, a pressure die, an accelerometer, a gyroscope, a microphone, a speaker, a transducer, an optical sensor, a gas sensor, a bolometer, a giant megnetoresistive sensor (GMR), a tunnel magnetoresistive (TMR) sensor, an environmental sensor, and a temperature sensor.