H01L21/78

SILICON CARBIDE SEMICONDUCTOR DEVICE
20180012957 · 2018-01-11 ·

A silicon carbide semiconductor device has a silicon carbide substrate and an insulating film. The silicon carbide substrate includes a termination region having a peripheral edge, and an element region surrounded by the termination region. The insulating film is provided on the termination region. The termination region includes a first impurity region having a first conductivity type, and a field stop region having the first conductivity type, being in contact with the first impurity region and having a higher impurity concentration than the first impurity region. The field stop region is at least partially exposed at the peripheral edge.

SILICON CARBIDE SEMICONDUCTOR DEVICE
20180012957 · 2018-01-11 ·

A silicon carbide semiconductor device has a silicon carbide substrate and an insulating film. The silicon carbide substrate includes a termination region having a peripheral edge, and an element region surrounded by the termination region. The insulating film is provided on the termination region. The termination region includes a first impurity region having a first conductivity type, and a field stop region having the first conductivity type, being in contact with the first impurity region and having a higher impurity concentration than the first impurity region. The field stop region is at least partially exposed at the peripheral edge.

Semiconductor device manufacturing method
11710731 · 2023-07-25 · ·

Provided is a technique suitable for multilayering thin semiconductor elements via adhesive bonding while avoiding wafer damage in a method of manufacturing a semiconductor device, the method in which semiconductor elements are multilayered through laminating wafers in which the semiconductor elements are fabricated. The method of the present invention includes bonding and removing. In the bonding step, a back surface 1b side of a thinned wafer 1T in a reinforced wafer 1R having a laminated structure including a supporting substrate S, a temporary adhesive layer 2, and the thinned wafer 1T is bonded via an adhesive to an element forming surface 3a of a wafer 3. A temporary adhesive for forming the temporary adhesive layer 2 contains a polyvalent vinyl ether compound, a compound having two or more hydroxy groups or carboxy groups and thus capable of forming a polymer with the polyvalent vinyl ether compound, and a thermoplastic resin. The adhesive contains a polymerizable group-containing polyorganosilsesquioxane. In the removing step, a temporary adhesion by the temporary adhesive layer 2 between the supporting substrate S and the thinned wafer 1T is released to remove the supporting substrate S.

Methods for multi-wafer stacking and dicing
11710717 · 2023-07-25 · ·

A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

Methods for multi-wafer stacking and dicing
11710717 · 2023-07-25 · ·

A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

DEPOSITION PROCESS MONITORING SYSTEM, AND METHOD OF CONTROLLING DEPOSITION PROCESS AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SYSTEM

Provided are a deposition process monitoring system capable of detecting an internal state of a chamber in a deposition process, and a method of controlling the deposition process and a method of fabricating a semiconductor device using the system. The deposition process monitoring system includes a facility cover configured to define a space for a deposition process, a chamber located in the facility cover, covered with a translucent cover dome, and having a support on which a deposition target is placed, a plurality of lamps disposed in the facility cover, the lamps respectively disposed above and below the chamber, the lamps configured to supply radiant heat energy into the chamber during the deposition process, and a laser sensor disposed outside the chamber, the laser sensor configured to irradiate the cover dome with a laser beam and detect an intensity of the laser beam transmitted through the cover dome, wherein a state of by-products with which the cover dome is coated is determined based on the detected intensity of the laser beam.

DEPOSITION PROCESS MONITORING SYSTEM, AND METHOD OF CONTROLLING DEPOSITION PROCESS AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SYSTEM

Provided are a deposition process monitoring system capable of detecting an internal state of a chamber in a deposition process, and a method of controlling the deposition process and a method of fabricating a semiconductor device using the system. The deposition process monitoring system includes a facility cover configured to define a space for a deposition process, a chamber located in the facility cover, covered with a translucent cover dome, and having a support on which a deposition target is placed, a plurality of lamps disposed in the facility cover, the lamps respectively disposed above and below the chamber, the lamps configured to supply radiant heat energy into the chamber during the deposition process, and a laser sensor disposed outside the chamber, the laser sensor configured to irradiate the cover dome with a laser beam and detect an intensity of the laser beam transmitted through the cover dome, wherein a state of by-products with which the cover dome is coated is determined based on the detected intensity of the laser beam.

Semiconductor packages and methods of packaging semiconductor devices

A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.

Semiconductor packages and methods of packaging semiconductor devices

A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.

GaN-on-Si SEMICONDUCTOR DEVICE STRUCTURES FOR HIGH CURRENT/ HIGH VOLTAGE LATERAL GaN TRANSISTORS AND METHODS OF FABRICATION THEREOF
20180012770 · 2018-01-11 ·

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.