A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall thickness of less than 0.2 mm and a thinned area surrounding the lens so that in the thinned area the wall thickness is reduced by at least 35%.

In examples, an electronic device comprises a printed circuit board (PCB), an orifice extending through the PCB, and a semiconductor die suspended above the orifice by aluminum bond wires. The semiconductor die is vertically aligned with the orifice and the bond wires coupled to the PCB.

A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

In a semiconductor apparatus, the apparatus is so arranged as to comprise: a semiconductor device having electrodes and wiring-interconnects on a main surface of a semiconductor chip; a first resin structure member, being placed on a side of the main surface of the semiconductor chip, constituting, in lateral and upward directions of a specific electrode of the semiconductor device, a hollow-body structure between the specific electrode and the first resin structure member; a second resin structure member covering an outer lateral side of the first resin structure member, and having the permittivity smaller than or equal to the permittivity of the first resin structure member; and an insulation film covering an outer lateral side of the second resin structure member, and having moisture permeability lower than that of the second resin structure member.

A semiconductor device includes a ground plane, a capacitor disposed on the ground plane and having a first top surface, a semiconductor chip disposed on the ground plane and having a second top surface, a bonding wire connecting the first top surface and the second top surface, and a conductive member disposed on the ground plane. The conductive member is electrically connected to the ground plane. The bonding wire extends in a first direction in a planar view normal to the ground plane. The conductive member is positioned apart from the bonding wire in a second direction orthogonally intersecting in the planar view with the first direction.

A semiconductor device (100) according to the present disclosure comprises a semiconductor chip (130) in which are formed a protruding terminal (14) that electrically connects to a transistor (13) and that has a greater cross-sectional area than a bonding wire (4) and a short circuit prevention side wall (15) that is insulating and that covers side surfaces that face the surroundings of the protruding terminal (14). The semiconductor chip (130) is bonded to the upper surface (3) of a metal plate (2) by a conductive bonding material 6. A conductor pattern (34a) that is formed in a circuit board (30) bonded to the upper surface (3) of the metal plate (2) is connected via the bonding wire (4) to the projection-direction end of the protruding terminal (14).

A package includes an electrically conductive carrier, an electronic component on the carrier, an encapsulant encapsulating part of the carrier and the electronic component, an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier, and a protection cap covering at least part of the interface structure. Corresponding methods of manufacturing and operating the package are also described.

Wafer level encapsulated packages includes a wafer, a glass substrate hermetically sealed to the wafer, and an electronic component. The glass substrate includes a glass cladding layer fused to a glass core layer and a cavity formed in the glass substrate. The electronic component is encapsulated within the cavity. In various embodiments, the floor of the cavity is planar and substantially parallel to a plane defined by a top surface of the glass cladding layer. The glass cladding layer has a higher etch rate in an etchant than the glass core layer. In various embodiments, the wafer level encapsulated package is substantially optically transparent. Methods for forming the wafer level encapsulated package and electronic devices formed from the wafer level encapsulated package are also described.

A device is provided. The device may include one or more of a package base, a substrate, a die secured to the substrate, a plurality of bond connections, and a package lid. The package base includes a plurality of package leads and a package base body. The package base body includes an open cavity disposed through the entire package base body, a plurality of package bond pads, disposed within a periphery of the open cavity, and a mounting shelf, disposed within the open cavity. The substrate is secured to the mounting shelf, and includes a plurality of substrate bond pads. The plurality of bond connections are configured to provide electrical connections between one or more of the die, the substrate bond pads, and the package bond pads. The package lid is secured over the open cavity to the package base body.

A semiconductor device according to an embodiment includes: an insulating substrate having a first metal layer and a second metal layer on a surface of the insulating substrate; a semiconductor chip including an upper electrode and a lower electrode, the upper electrode being electrically connected to the first metal layer, the lower electrode being electrically connected to the second metal layer; a first main terminal including a first end and a second end, the first end being electrically connected to the first metal layer; a second main terminal including a third end and a fourth end, the third end being electrically connected to the second metal layer; a first detection terminal being electrically connected between the first end and the second end of the first main terminal; and a second detection terminal being electrically connected to the first metal layer.