A power electronics module includes an electrically-conductive substrate including a base portion defining a plurality of orifices that extend through the base portion, the plurality of orifices defining a plurality of jet paths extending along and outward from the plurality of orifices, and a plurality of posts extending outward from the base portion, where individual posts of the plurality of posts are positioned between individual orifices of the plurality of orifices, and a power electronics device coupled to the plurality of posts opposite the base portion, the power electronics device defining a bottom surface that is oriented transverse to the plurality of jet paths.

A semiconductor device includes a ground plane, a capacitor disposed on the ground plane and having a first top surface, a semiconductor chip disposed on the ground plane and having a second top surface, a bonding wire connecting the first top surface and the second top surface, and a conductive member disposed on the ground plane. The conductive member is electrically connected to the ground plane. The bonding wire extends in a first direction in a planar view normal to the ground plane. The conductive member is positioned apart from the bonding wire in a second direction orthogonally intersecting in the planar view with the first direction.

A power semiconductor device includes a casing, a first insulating circuit board, a second insulating circuit board, and a sealing material. The first insulating circuit board is disposed to be surrounded by the casing. The second insulating circuit board is surrounded by the casing and spaced from the first insulating circuit board so as to sandwich a semiconductor element between the first insulating circuit board and the second insulating circuit board. The sealing material fills a region surrounded by the casing. The first or second insulating circuit board is provided with a hole extending from one main surface to the other main surface opposite to one main surface. From at least a portion of an inner wall surface of the casing a protrusion extending to a region overlapping the first or second insulating circuit board in a plan view extends toward the region surrounded by the casing.

On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.

Aspects of the present disclosure include one or more power semiconductor device modules. A power semiconductor module can include: a power terminal, a housing, a heatsink and a protrusion, wherein the housing includes a first tab, and a first protrusion, and wherein the first tab contacts the substrate, and the first protrusion contacts the heatsink.

A package includes an electrically conductive carrier, an electronic component on the carrier, an encapsulant encapsulating part of the carrier and the electronic component, an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier, and a protection cap covering at least part of the interface structure. Corresponding methods of manufacturing and operating the package are also described.

A semiconductor device includes: a semiconductor chip; a case storing the semiconductor chip; a wire bonded to the semiconductor chip; a cover fixed inside the case and including a concave portion disposed above the semiconductor chip and the wire; and a sealing resin potted inside the case and sealing the semiconductor chip, the wire and the cover, wherein the sealing resin is not filled in the concave portion so that a cavity is provided.

A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

A semiconductor device includes a conductive can include a flat portion and at least one peripheral rim portion extending from an edge of the flat portion, a semiconductor die comprising a first main face and a second main face opposite to the first main face, a first contact pad disposed on the first main face and a second contact pad disposed on the second main face, wherein the first contact pad is electrically connected to the flat portion of the can, an electrical interconnector connected with the second contact pad, and an encapsulant disposed under the semiconductor die so as to surround the electrical interconnector, wherein an external surface of the electrical interconnector is recessed from an external surface of the encapsulant.