Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

In a semiconductor apparatus, the apparatus is so arranged as to comprise: a semiconductor device having electrodes and wiring-interconnects on a main surface of a semiconductor chip; a first resin structure member, being placed on a side of the main surface of the semiconductor chip, constituting, in lateral and upward directions of a specific electrode of the semiconductor device, a hollow-body structure between the specific electrode and the first resin structure member; a second resin structure member covering an outer lateral side of the first resin structure member, and having the permittivity smaller than or equal to the permittivity of the first resin structure member; and an insulation film covering an outer lateral side of the second resin structure member, and having moisture permeability lower than that of the second resin structure member.

A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

A power electronics module includes an electrically-conductive substrate including a base portion defining a plurality of orifices that extend through the base portion, the plurality of orifices defining a plurality of jet paths extending along and outward from the plurality of orifices, and a plurality of posts extending outward from the base portion, where individual posts of the plurality of posts are positioned between individual orifices of the plurality of orifices, and a power electronics device coupled to the plurality of posts opposite the base portion, the power electronics device defining a bottom surface that is oriented transverse to the plurality of jet paths.

Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

An integrated circuit (IC) die (100) is disclosed having a major surface delimited by at least one edge (102) of the IC die, said major surface carrying a plurality of electrically conductive contact plates (130) extending from said major surface beyond the at least one edge such that each contact plate includes an exposed contact surface portion (132) delimited by the at least one edge for mating with an electrically conductive further contact surface portion (230) on at least one further edge (220) of a body (200), said at least one further edge delimiting a cavity for receiving the IC die. An ultrasound probe including such an IC die and a method of providing such an IC die with contacts are also disclosed.

A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.