An example includes: a substrate having a first package surface, having a second package surface opposite the first package surface, and having a die cavity with a depth extending into the first package surface; a semiconductor die having bond pads on a first die surface and having a second die surface opposite the first die surface, the semiconductor die having a die thickness, the second die surface of the semiconductor die mounted in the die cavity; a cover over a portion of the first die surface; conductors coupling the bond pads of the semiconductor die to bond fingers on the first package surface of the substrate; and dielectric material over the conductors, the bond fingers, the bond pads, at least a portion of the first semiconductor die and at least a portion of the cover, wherein the dielectric material extends above the first package surface of the substrate.

The present invention provides a power semiconductor module, including a substrate having an electric insulating main layer being provided with a structured top metallization and with a bottom metallization, wherein the top metallization is provided with at least one power semiconductor device and at least one contact area, wherein the main layer together with its top metallization and the at least one power semiconductor device is embedded in a mold compound such that the mold compound includes at least one opening for contacting the at least one contact area, and wherein power semiconductor module includes a housing with circumferential side walls, wherein the side walls are positioned above the main layer of the substrate so that the side walls are only present in a space above a plane through the main layer of the substrate.

The present invention provides a power semiconductor module, including a substrate having an electric insulating main layer being provided with a structured top metallization and with a bottom metallization, wherein the top metallization is provided with at least one power semiconductor device and at least one contact area, wherein the main layer together with its top metallization and the at least one power semiconductor device is embedded in a mold compound such that the mold compound includes at least one opening for contacting the at least one contact area, and wherein power semiconductor module includes a housing with circumferential side walls, wherein the side walls are positioned above the main layer of the substrate so that the side walls are only present in a space above a plane through the main layer of the substrate.

A light emitting device including a fluorescent material with reduced hue, and a method of manufacturing the light emitting device are provided. A light emitting device 100 includes: a light emitting element 1; a first light-transmissive member 3 covering the light emitting element 1; and a light diffusing member 5 contained in the first light-transmissive member 3. The light diffusing member 5 includes hollow particles. The surface of the first light-transmissive member 3 has irregular shapes attributed to the light diffusing member 5. The first light-transmissive member 3 is covered with a second light-transmissive member 4. The second light-transmissive member 4 has a convex structure in which the center is the uppermost point. The irregular shapes attributed to the light diffusing member 5 are covered with the second light-transmissive member 4.

In a crystal oscillator, a crystal resonator and an IC chip are hermetically sealed in a package. The crystal resonator includes: a crystal resonator plate including a first excitation electrode formed on a first main surface, and a second excitation electrode, which makes a pair with the first excitation electrode, formed on a second main surface; a first sealing member covering the first excitation electrode of the crystal resonator plate; and a second sealing member covering the second excitation electrode of the crystal resonator plate. A vibrating part including the first excitation electrode and the second excitation electrode of the crystal resonator plate is hermetically sealed by bonding the first sealing member to the crystal resonator plate, and the second sealing member to the crystal resonator plate.

In a crystal oscillator, a crystal resonator and an IC chip are hermetically sealed in a package. The crystal resonator includes: a crystal resonator plate including a first excitation electrode formed on a first main surface, and a second excitation electrode, which makes a pair with the first excitation electrode, formed on a second main surface; a first sealing member covering the first excitation electrode of the crystal resonator plate; and a second sealing member covering the second excitation electrode of the crystal resonator plate. A vibrating part including the first excitation electrode and the second excitation electrode of the crystal resonator plate is hermetically sealed by bonding the first sealing member to the crystal resonator plate, and the second sealing member to the crystal resonator plate.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.

A semiconductor device, including a semiconductor chip, a case having an opening formed therein and an inner wall communicating with the opening, and a sealing member. The inner wall surrounds a housing space for accommodating the semiconductor chip. The sealing member fills the housing space to seal the semiconductor chip. The sealing member has a side surface and a sealing surface. The side surface has a contact area contacting the inner wall of the case. The contact area is positioned, in a depth direction of the semiconductor device, closer to the semiconductor chip than is the sealing surface of the sealing member.

A semiconductor device, including a semiconductor chip, a case having an opening formed therein and an inner wall communicating with the opening, and a sealing member. The inner wall surrounds a housing space for accommodating the semiconductor chip. The sealing member fills the housing space to seal the semiconductor chip. The sealing member has a side surface and a sealing surface. The side surface has a contact area contacting the inner wall of the case. The contact area is positioned, in a depth direction of the semiconductor device, closer to the semiconductor chip than is the sealing surface of the sealing member.