A semiconductor package includes semiconductor elements, a lead frame, a crosslinked member, and sealing resin. Each of the semiconductor elements has a first surface and a second surface located on a side opposite to the first surface. The lead frame has a mounting portion and a connected portion. At least one of the semiconductor elements mounts on the mounting portion. The connected portion is separated from the mounting portion. The crosslinked member is connected to the second surface of at least one of the semiconductor elements and the connected portion to electrically connect at least one of the semiconductor elements and the connected portion. The sealing resin is electrically insulated and covers a portion of the lead frame, the semiconductor elements and the crosslinked member. At least one of the semiconductor elements is different from another one of the semiconductor elements in element size or power consumption.

Embodiments of a microelectronic assembly comprise an integrated circuit (IC) die and a package substrate having a core and redistribution layers on either side of the core. The IC die is coupled to a face of the package substrate, the face being parallel to the core. The core comprises one of glass, ceramic, and metal. The redistribution layers comprise one or more layers of a dielectric material, with conductive traces adjacent to the one or more layers of the dielectric material and conductive vias through the one or more layers of the dielectric material. The core comprises a hollow channel.

Embodiments of a microelectronic assembly comprise an integrated circuit (IC) die and a package substrate having a core and redistribution layers on either side of the core. The IC die is coupled to a face of the package substrate, the face being parallel to the core. The core comprises one of glass, ceramic, and metal. The redistribution layers comprise one or more layers of a dielectric material, with conductive traces adjacent to the one or more layers of the dielectric material and conductive vias through the one or more layers of the dielectric material. The core comprises a hollow channel.

A housing for at least one electronic device includes: a base part including a mounting area for the at least one electronic device; a lid made of glass, the lid made of glass having at least one window integrated therein that is made of a material transparent to infrared radiation; a first mounting area which is arranged under a portion of the lid made of glass; and a second mounting area arranged under the at least one window.

A housing for at least one electronic device includes: a base part including a mounting area for the at least one electronic device; a lid made of glass, the lid made of glass having at least one window integrated therein that is made of a material transparent to infrared radiation; a first mounting area which is arranged under a portion of the lid made of glass; and a second mounting area arranged under the at least one window.

A semiconductor package in an aspect of the present invention includes a metal board, a first frame, a second frame, and a bond. The metal board has an upper surface including a mount on which a semiconductor device is mountable. The first frame has a side surface facing a side surface of the metal board and has a smaller thermal expansion coefficient than the metal board. The second frame is on upper surfaces of the metal board and the first frame and surrounds the mount, and has a smaller thermal expansion coefficient than the metal board. The bond is between the metal board and the first frame, between the metal board and the second frame, and between the first frame and the second frame. The semiconductor package includes an alloy layer between the metal board and the bond.

A semiconductor package in an aspect of the present invention includes a metal board, a first frame, a second frame, and a bond. The metal board has an upper surface including a mount on which a semiconductor device is mountable. The first frame has a side surface facing a side surface of the metal board and has a smaller thermal expansion coefficient than the metal board. The second frame is on upper surfaces of the metal board and the first frame and surrounds the mount, and has a smaller thermal expansion coefficient than the metal board. The bond is between the metal board and the first frame, between the metal board and the second frame, and between the first frame and the second frame. The semiconductor package includes an alloy layer between the metal board and the bond.

Circuits are added while an increase in size of a semiconductor package is prevented. The semiconductor package includes a transparent member; an embedding resin; an embedded circuit; and a solid-state image pickup element. In the semiconductor package, the embedding resin is formed around the transparent member. Further, in the semiconductor package, the embedded circuit is embedded in the embedding resin. Further, in the semiconductor package, the solid-state image pickup element performs photoelectric conversion on light that has passed through the transparent member and thereby generates image data.

A substrate stack includes: at least two substrates including a base substrate and a cover substrate; at least one first laser weld line for welding the base substrate and the cover substrate; and at least one second beam spot or at least one second laser weld line at least one of situated next to the at least one first laser weld line or positioned such that a stress reduction in the at least one first laser weld line is achieved by the at least one second beam spot or second laser weld line, thus improving the mechanical stability of the substrate stack.

A substrate stack includes: at least two substrates including a base substrate and a cover substrate; at least one first laser weld line for welding the base substrate and the cover substrate; and at least one second beam spot or at least one second laser weld line at least one of situated next to the at least one first laser weld line or positioned such that a stress reduction in the at least one first laser weld line is achieved by the at least one second beam spot or second laser weld line, thus improving the mechanical stability of the substrate stack.