Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.

Techniques for self-assembly of regions in a dielectric layer with different electrical properties are described herein. In one example, a package includes a substrate, a layer of dielectric material over the substrate, the layer of dielectric material including a filler material. The package includes a plurality of conductive traces in the layer of dielectric material, and a filler-depleted radial region of the dielectric material around each of the plurality of conductive traces. The filler-depleted radial region has a lower volume-percentage of filler than other regions of the layer of dielectric material. In one example, the conductive traces, filler, or both include a coating to cause the filler and traces to have opposing surface chemistry.

Semiconductor devices having hollow filler materials are disclosed. A disclosed example semiconductor device includes at least one of a substrate or an interposer, interconnects extending through the at least one of the substrate or the interposer, and a composite material integral with or covering at least a portion of the semiconductor device, the composite material including a polymer matrix with a hollow filler material having voids therein.

A semiconductor device includes an insulating substrate, a first and a second obverse-surface metal layers disposed on an obverse surface of the insulating substrate, a first and a second reverse-surface metal layers disposed on a reverse surface of the insulating substrate, a first conductive layer and a first semiconductor element disposed on the first obverse-surface metal layer, and a second conductive layer and a second semiconductor element disposed on the second obverse-surface metal layer. Each of the first conductive layer and the second conductive layer has an anisotropic coefficient of linear expansion and is arranged such that the direction in which the coefficient of linear expansion is relatively large is along a predetermined direction perpendicular to the thickness direction of the insulating substrate. The first and second reverse-surface metal layers are smaller than the first and second obverse-surface metal layers in dimension in the predetermined direction.

The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.

An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

A method for manufacturing a printed wiring board which includes: Step (A) of laminating an adhesive sheet including a support and a resin composition layer bonded to the support to an inner layer board so that the resin composition layer is bonded to the inner layer board; Step (B) of thermally curing the resin composition layer to form an insulating layer; and Step (C) of removing the support, in this order, in which the support satisfies a condition (MD1): a maximum expansion coefficient E.sub.MD in an MD direction at 120° C. or more is less than 0.2% and a condition (TD1): a maximum expansion coefficient E.sub.TD in a TD direction at 120° C. or more is less than 0.2% below, when being heated under predetermined heating conditions, does not lower the yield even when the insulating layer is formed by thermally curing the resin composition layer with a support attached to the resin composition layer.

A packaged integrated circuit includes a core structure with a cavity therein; a component accommodated in the cavity; an electrically insulating structure formed over the core structure and the component; a partially electrically insulating carrier structure formed below the core structure and the component; and an electrically conducting redistribution arrangement formed at least partially within the carrier structure. The redistribution arrangement includes conductor structures each having a first element extending through the carrier structure and electrically connecting a contact of the component and a second element below the carrier structure. A part of the second element is a contact pad for electrically connecting the redistribution arrangement with external circuitry. The carrier structure includes a polyimide layer and an adhesive layer. The adhesive layer is directly attached to an upper surface of the polyimide layer and to a lower surface of the core structure and a lower surface of the component.

An apparatus is provided that includes a thin-film interconnect structure that comprises one or more polymeric layers and conductive plating, a first surface of the thin-film interconnect structure being configured to receive one or more dies, and a second surface of the thin-film interconnect structure being configured to receive a substrate. A method of assembling the apparatus into an integrated circuit assembly is also provided.

A miniaturized and high-power semiconductor package device with its own heat-dissipating ability includes a heat conducting carrier, a redistribution layer, an electronic device, electronic components, a molding layer, and a solder ball. The heat conducting carrier includes an opening. The redistribution layer is formed on the heat conducting carrier. The redistribution layer has a circuit layer. The electronic device and the electronic components are disposed on a first surface of the redistribution layer away from the heat conducting carrier. The molding layer surrounds the electronic device and covers the electronic component. The solder balls are disposed in the opening, are in contact with a second surface of the redistribution layer opposite to the first surface, and are electrically connected to the circuit layer.