A flexible passive electronic component includes a substrate, which comprises an insulating layer and optionally an inorganic layer with an upper side and a lower side, whereby the insulating layer at least partially covers the upper side of the optional inorganic layer. The flexible passive electronic component further comprises an electrical structure at least partially covering the insulating layer. The substrate has a thickness, which is at most 500 μm. The flexible passive electronic component has a height, which is at most 150 11 μm.

A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

A semiconductor package includes a package substrate, an encapsulated semiconductor device, and a plurality of conductive bumps. The package substrate includes a device mounting region, a plurality of substrate pads and a solder resist layer. The encapsulated semiconductor device is disposed over the device mounting region and includes a plurality of device pads. The conductive bumps are connected between the plurality of substrate pads and the plurality of device pads through the solder resist layer and includes a first conductive bump on a periphery of the device mounting region. A first contact area of the first conductive bump for contacting respective one of the substrate pads is substantially greater than a second contact area of the first conductive bump for contacting respective one of the device pads.

A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.

A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.

A semiconductor device includes an integrated circuit, first conductive features, second conductive features, a package structure, and an encapsulant. The integrated circuit has an active surface and a rear surface opposite to the active surface. The first conductive features surround the integrated circuit. The second conductive features are stacked on the first conductive features. The package structure is disposed on the second conductive features and the rear surface of the integrated circuit. The encapsulant laterally encapsulates the integrated circuit, the first conductive features, the second conductive features, and the package structure.

An integrated circuit package comprising one or more electronic component(s); a first substrate including a first surface and a second surface of the first substrate; and a second substrate including a first surface and a second surface of the second substrate. The first substrate including a first first-substrate cavity on the first surface of the first substrate. The second substrate includes a first second-substrate cavity on the first surface of the second substrate. The second surface of the first substrate and the second surface of the second substrate is located between the first surface of the first substrate and the first surface of the second substrate; or the first surface of the first substrate and the first surface of the second substrate is located between the second surface of the first substrate and the second surface of the second substrate.

Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die.

In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.