A nitride semiconductor device includes a substrate; a nitride semiconductor multilayer structure which is formed on the substrate, includes a first nitride semiconductor layer and a second nitride semiconductor layer having a different composition from that of the first nitride semiconductor layer, and generates two dimensional electron gas on a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and an insulating film which covers at least a portion of a surface of the nitride semiconductor multilayer structure, has a concentration of Si—H bonds equal to or less than 6.0×10.sup.21 cm.sup.−3, and is formed of silicon nitride.

A three-terminal nano-electro-mechanical field-effect transistor (NEMFET) includes a source electrode, a gate electrode, a drain electrode and a nanoelectromechanically suspended channel bridging the source electrode and the drain electrode. The nanoelectromechanically suspended channel includes a moveable nanowire and a dielectric coating on a surface of the nanowire facing the gate electrode. A thickness of a gap between the nanowire and the gate electrode is determined by a thickness of the dielectric coating.

The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor devices, passivation of semiconductor surfaces, semiconductor etching and anti-reflective coatings for semiconductor devices.

A semiconductor device includes: a semiconductor element disposed on a semiconductor substrate; a first insulating film disposed on the semiconductor substrate, the first insulating film having an upper surface and an edge; a resin layer disposed on the semiconductor substrate, the resin layer covering the semiconductor element; and a second insulating film disposed on the semiconductor substrate, the second insulating film covering the upper and side surfaces of the resin layer, wherein the second insulating film has an edge arranged apart from the side surface of the resin layer by a distance, and the distance between the edge of the second insulating film and the side surface of the resin layer is greater than a film thickness of the second insulating film.

A printed circuit module and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and a buried oxide (BOX) layer over the at least one device layer. A polymer layer is disposed over the BOX layer, wherein the polymer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10.sup.3 Ohm-cm.

Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

A substrate oxidation assembly includes: a chamber body defining a processing volume; a substrate support disposed in the processing volume; a plasma source coupled to the processing volume; a steam source fluidly coupled to the processing volume; and a substrate heater. A method of processing a semiconductor substrate includes: initiating conformal radical oxidation of high aspect ratio structures of the substrate comprising: heating the substrate; and exposing the substrate to steam; and conformally oxidizing the substrate. A semiconductor device includes a silicon and nitrogen containing layer; a feature formed in the silicon and nitrogen containing layer having an aspect ratio of at least 40:1; and an oxide layer on the face of the feature having a thickness in a bottom region of the silicon and nitrogen containing layer that is at least 95% of a thickness of the oxide layer in a top region.

A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

A semiconductor device is provided, including a substrate, an interconnection structure formed on the substrate, a first top conductive layer formed on the interconnection structure, bars formed on the interconnection structure, and a second top conductive layer formed above the first top conductive layer. The first top conductive layer includes several first conducting portions spaced apart from each other, and at least one of the bars is positioned between adjacent two of the first conducting portions.