A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

The technology of this application relates to a semiconductor packaged structure, including a circuit board, a chip, a pin, and a plastic package body. The pin includes a connecting part and a pressfit, one end of the connecting part is welded to the circuit board, the other end is flush with a top surface of the plastic package body, the connecting part has a mounting hole, the pressfit is disposed in the mounting hole and is in an interference fit with the connecting part, the pressfit is exposed from the top surface of the plastic package body. Alternatively, the pin includes a pressfit, the plastic package body is provided with a mounting hole that runs through a plastic package body, the pressfit is provided in the mounting hole, one end of the pressfit is welded to the circuit board, the other end is exposed from the top surface of the plastic package body.

A microelectronic assembly having a first side and a second side opposite therefrom is disclosed. The microelectronic assembly may include a microelectronic element having a first face, a second face opposite the first face, a plurality of sidewalls each extending between the first and second faces, and a plurality of element contacts. The microelectronic assembly may also include an encapsulation adjacent the sidewalls of the microelectronic element. The microelectronic assembly may include electrically conductive connector elements each having a first end, a second end remote from the first end, and an edge surface extending between the first and second ends, wherein one of the first end or the second end of each connector element is adjacent the first side of the package. The microelectronic assembly may include a redistribution structure having terminals, the redistribution structure adjacent the second side of the package, the terminals being electrically coupled with the connector elements.

A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

A semiconductor device and a lead frame. The semiconductor device comprises at least one semiconductor chip that is attached to a surface of a base island in a first plane, wherein a connecting rib is connected to the base island, and has a first part which is obliquely connected to the base island; the connecting rib has a second part, and the second part has a surface in a second plane; the second plane is parallel to the first plane and is a plane different from the first plane; the connecting rib has a branch part divided from the second part and the branch part has, in the second plane, a surface used for receiving a lead connected to the semiconductor chip; and the branch part has an edge which is distant from a first edge of the base island by a first distance.

A semiconductor device includes a sealing resin being an insulating resin sealing the semiconductor element therein, and a plurality of electrode terminals each including a root portion being a root protruding from the sealing resin, a tip portion being a tip and portion extending from the root portion, and a middle portion provided between the tip portion and the root portion, and the middle portion includes first middle portions having a width wider than those of the root portion and the tip portion in the first direction, and a second middle portion having a width wider than those of the root portion and the tip portion in the first direction, a width narrower than those of the first middle portions in the first direction, and a bent portion bent toward in a third direction orthogonal to the first direction and the second direction.

A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.

Semiconductor chips to be singulated to individual semiconductor devices are arranged onto respective adjacent areas of a mounting substrate such as a pre-molded leadframe. The mounting substrate is made of a laminar, electrically conductive sculptured structure with molded electrically insulating material. Electrically conductive side formations in the adjacent areas of the mounting substrate include first and second pads at front and back surfaces, respectively, of the mounting substrate. The first contact pads at the front surface of the substrate include narrowed portions having side recesses. The second contact pads at the back surface of the substrate include widened portions having side extensions adjacent the side recesses. The electrically insulating material extends into the side recesses to provide anchoring formations of the insulating material to the electrically conductive sculptured structure of the mounting substrate.